ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
H.7.11 c9, cache lockdown support
One problem with caches is that although they normally improve average access time to data and
instructions, they usually increase the worst-case access time. This is because:
There is a delay before the system determines that a cache miss has occurred and starts the main
memory access.
If a Write-Back cache is being used, there might be more delay because of the requirement to store
the contents of the cache line that is being reallocated.
A whole cache line is loaded from main memory, not only the data requested by the ARM processor.
In real-time applications, this increase in the worst-case access time can be significant.
Cache lockdown is an optional feature designed to alleviate this. It enables critical code and data, for
example high priority interrupt routines and the data they access, to be loaded into the cache in such a way
that the cache lines containing them are not subsequently reallocated. This ensures that all subsequent
accesses to this code and data are cache hits and therefore complete as quickly as possible.
The ARM architecture specifies four formats for the cache lockdown mechanism. These are known as
Format A, Format B, Format C, and Format D. The Cache Type Register contains information on the
lockdown mechanism adopted. See c0, Cache Type Register (CTR) on page AppxH-35.
Formats A, B, and C all operate on cache ways. Format D is a cache entry locking mechanism. Table H-24
summarizes the CP15 provisions for format A, B, C, and D lockdown mechanisms.
From ARMv7, cache lockdown is IMPLEMENTATION DEFINED with no recommended formats or
mechanisms on how it is achieved other than reserved CP15 register space. See Cache lockdown on
page B2-8 and CP15 c9, Cache and TCM lockdown registers and performance monitors on page B3-141.
Register or operation
Table H-23 TLB operation support (continued)
Operation CRn opc1 CRm opc2
Invalidate Data TLB Entry (by MVA) c8 0 c6 1
Invalidate Unified TLB c8 0 c7 0
Invalidate Unified TLB Entry (by MVA) c8 0 c7 1
Table H-24 cache lockdown register support
Lockdown
formats
CRn opc1 CRm opc2
Data or unified Cache Lockdown Register, DCLR A, B, and C c9 0 c0 0
Instruction Cache Lockdown Register, ICLR A, B, and C c9 0 c0 1
Fetch and lock instruction cache line D c9 0 c5 0
AppxH-52 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B