ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
011 X X Reserved. - -
1BB A A Cacheable memory: AA = Inner attributec BB = Outer policy
a. Region is Shareable if S == 1, and Non-shareable if S == 0.
b. IMP. DEF. = IMPLEMENTATION DEFINED.
c. For more information see Cacheable memory attributes.
For an explanation of Normal, Strongly-ordered and Device memory types, and the Shareable attribute, see
Memory types and attributes and the memory order model on page A3-24.
Cacheable memory attributes
Table B4-4 C, B and TEX[2:0] encodings (continued)
TEX[2:0] C B Description Memory type Shareable?
Normal S bit a
When TEX[2] == 1, the memory region is Cacheable memory, and the rest of the encoding defines the Inner
and Outer cache attributes:
TEX[1:0] defines the Outer cache attribute
C,B defines the Inner cache attribute
The same encoding is used for the Outer and Inner cache attributes. Table B4-5 shows the encoding.
Table B4-5 Inner and Outer cache attribute encoding
Memory attribute encoding Cache attribute
00 Non-cacheable
01 Write-Back, Write-Allocate
10 Write-Through, no Write-Allocate
11 Write-Back, no Write-Allocate
B4-12 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B