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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Introduction to the <strong>ARM</strong> <strong>Architecture</strong><br />

A1.4 <strong>Architecture</strong> extensions<br />

This manual describes the following extensions to the <strong>ARM</strong> <strong>and</strong> Thumb instruction set architectures:<br />

ThumbEE Is a variant of the Thumb instruction set that is designed as a target for dynamically<br />

generated code. It is:<br />

a required extension to the <strong>ARM</strong>v7-A profile<br />

an optional extension to the <strong>ARM</strong>v7-R profile.<br />

VFP Is a floating-point coprocessor extension to the instruction set architectures. There<br />

have been three main versions of VFP to date:<br />

VFPv1 is obsolete. Details are available on request from <strong>ARM</strong>.<br />

VFPv2 is an optional extension to:<br />

— the <strong>ARM</strong> instruction set in the <strong>ARM</strong>v5TE, <strong>ARM</strong>v5TEJ, <strong>ARM</strong>v6, <strong>and</strong><br />

<strong>ARM</strong>v6K architectures<br />

— the <strong>ARM</strong> <strong>and</strong> Thumb instruction sets in the <strong>ARM</strong>v6T2 architecture.<br />

VFPv3 is an optional extension to the <strong>ARM</strong>, Thumb <strong>and</strong> ThumbEE<br />

instruction sets in the <strong>ARM</strong>v7-A <strong>and</strong> <strong>ARM</strong>v7-R profiles.<br />

VFPv3 can be implemented with either thirty-two or sixteen doubleword<br />

registers, as described in Advanced SIMD <strong>and</strong> VFP extension registers on<br />

page A2-21. Where necessary, the terms VFPv3-D32 <strong>and</strong> VFPv3-D16 are<br />

used to distinguish between these two implementation options. Where the<br />

term VFPv3 is used it covers both options.<br />

VFPv3 can be extended by the half-precision extensions that provide<br />

conversion functions in both directions between half-precision floating-point<br />

<strong>and</strong> single-precision floating-point.<br />

Advanced SIMD Is an instruction set extension that provides Single Instruction Multiple Data<br />

(SIMD) functionality. It is an optional extension to the <strong>ARM</strong>v7-A <strong>and</strong> <strong>ARM</strong>v7-R<br />

profiles. When VFPv3 <strong>and</strong> Advanced SIMD are both implemented, they use a<br />

shared register bank <strong>and</strong> have some shared instructions.<br />

Advanced SIMD can be extended by the half-precision extensions that provide<br />

conversion functions in both directions between half-precision floating-point <strong>and</strong><br />

single-precision floating-point.<br />

Security Extensions Are a set of security features that facilitate the development of secure applications.<br />

They are an optional extension to the <strong>ARM</strong>v6K architecture <strong>and</strong> the <strong>ARM</strong>v7-A<br />

profile.<br />

Jazelle Is the Java bytecode execution extension that extended <strong>ARM</strong>v5TE to <strong>ARM</strong>v5TEJ.<br />

From <strong>ARM</strong>v6 Jazelle is a required part of the architecture, but is still often<br />

described as the Jazelle extension.<br />

Multiprocessing Extensions<br />

Are a set of features that enhance multiprocessing functionality. They are an<br />

optional extension to the <strong>ARM</strong>v7-A <strong>and</strong> <strong>ARM</strong>v7-R profiles.<br />

A1-6 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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