ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
If the system implements any data or unified caches that can be accessed by the processor
then it must be possible to disable them by setting this bit to 0.
A, bit [1] Alignment bit. This is the enable bit for Alignment fault checking:
0 Alignment fault checking disabled
1 Alignment fault checking enabled.
For more information, see Alignment on page AppxH-6.
M, bit [0] Memory control bit. This is a global enable bit to enable an MMU where VMSA is
supported, or an MPU where PMSA is supported:
0 memory management (MMU or MPU) disabled
1 memory management (MMU or MPU) enabled.
H.7.5 c2 and c3, VMSA memory protection and control registers
ARMv4 and ARMv5 support a single Translation Table Base Register (TTBR) that is compatible with
TTBR0, and the Domain Access Control Register (DACR).
The TTBR is as defined for TTBR0 in CP15 c2, Translation table support registers on page B3-113 except
that:
The base address bitfield is a fixed-length field, bits [31:14] (N=0)
Bit [5] is reserved.
The DACR is as defined in c3, Domain Access Control Register (DACR) on page B3-119.
H.7.6 c5 and c6, VMSA memory system support
ARMv4 and ARMv5 support a Fault Status Register (FSR) and a Fault Address Register (FAR). These
registers are accessed using MCR and MRC instructions. Table H-17 summarizes them.
Table H-17 VMSA fault support
Register CRn opc1 CRm opc2
Fault Status Register, FSR c5 0 c0 0
Fault Address Register, FAR c6 0 c0 0
The FSR is updated on Prefetch Abort exceptions and Data Abort exceptions. The FAR is only updated with
the MVA on Data Abort exceptions.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-41