ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Chapter A1 Introduction to the ARM Architecture This chapter introduces the ARM architecture and contains the following sections: About the ARM architecture on page A1-2 The ARM and Thumb instruction sets on page A1-3 Architecture versions, profiles, and variants on page A1-4 Architecture extensions on page A1-6 The ARM memory model on page A1-7 Debug on page A1-8. ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A1-1
Page 1 and 2: ® ARM Architecture Reference Manua
Page 3 and 4: This ARM Architecture Reference Man
Page 5 and 6: Contents ARM Architecture Reference
Page 7 and 8: Contents Chapter A6 Thumb Instructi
Page 9 and 10: Contents C1.3 Security Extensions a
Page 11 and 12: Contents Appendix D Deprecated and
Page 13 and 14: Preface This preface summarizes the
Page 15 and 16: Using this manual The information i
Page 17 and 18: Part D, Appendices This manual cont
Page 19 and 20: Assembler syntax descriptions This
Page 21 and 22: Feedback ARM welcomes feedback on i
Page 23: Part A Application Level Architectu
Page 27 and 28: A1.2 The ARM and Thumb instruction
Page 29 and 30: Introduction to the ARM Architectur
Page 31 and 32: A1.5 The ARM memory model Introduct
Page 33 and 34: Chapter A2 Application Level Progra
Page 35 and 36: A2.2 ARM core data types and arithm
Page 37 and 38: Shift and rotate operations The fol
Page 39 and 40: ROR() // ===== bits(N) ROR(bits(N)
Page 41 and 42: Pseudocode details of saturation Ap
Page 43 and 44: A2.3 ARM core registers In the appl
Page 45 and 46: BXWritePC() // =========== BXWriteP
Page 47 and 48: A2.5 Execution state registers The
Page 49 and 50: A2.5.2 ITSTATE Application Level Pr
Page 51 and 52: A2.5.3 ENDIANSTATE Application Leve
Page 53 and 54: Note Application Level Programmers
Page 55 and 56: The mapping between the registers i
Page 57 and 58: A2.6.2 Data types supported by the
Page 59 and 60: 127 0 Pseudocode details of Advance
Page 61 and 62: AHP, bit[26] Alternative half-preci
Page 63 and 64: A2.6.5 VFPv3U Accessing the FPSCR A
Page 65 and 66: A2.7.1 ARM standard floating-point
Page 67 and 68: exponent == 0xFF Application Level
Page 69 and 70: exponent == 0x7FF fraction != 0 The
Page 71 and 72: exponent == 0x1F A2.7.5 Flush-to-ze
Page 73 and 74: Note Application Level Programmers
Page 75 and 76:
Application Level Programmers’ Mo
Page 77 and 78:
Page 79 and 80:
FPInfinity() // ============ Applic
Page 81 and 82:
Page 83 and 84:
else done = FALSE; result = Zeros(N
Page 85 and 86:
StandardFPSCRValue() // ===========
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Maximum and minimum // FPMax() // =
Page 89 and 90:
Multiplication and division // FPMu
Page 91 and 92:
Call C function to get reciprocal e
Page 93 and 94:
Reciprocal square root Application
Page 95 and 96:
The Newton-Raphson iteration: xn+1
Page 97 and 98:
Page 99 and 100:
A2.8 Polynomial arithmetic over {0,
Page 101 and 102:
A2.10 Execution environment support
Page 103 and 104:
ThumbEE Handler Base Register (TEEH
Page 105 and 106:
A2.10.2 Jazelle direct bytecode exe
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
EJVM operation Application Level Pr
Page 113 and 114:
A2.11 Exceptions, debug events and
Page 115 and 116:
Chapter A3 Application Level Memory
Page 117 and 118:
Application Level Memory Model This
Page 119 and 120:
A3.2.1 Unaligned data access Instru
Page 121 and 122:
A3.3 Endian support The rules in Ad
Page 123 and 124:
Application Level Memory Model For
Page 125 and 126:
Note Application Level Memory Model
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Application Level Memory Model The
Page 129 and 130:
Note For the local monitor state ma
Page 131 and 132:
Application Level Memory Model If n
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Table A3-7 shows the effect of the
Page 135 and 136:
A3.4.4 Context switch support Appli
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A3.4.6 Semaphores Application Level
Page 139 and 140:
Application Level Memory Model Syst
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Single-copy atomicity A read or wri
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Application Level Memory Model writ
Page 145 and 146:
Application Level Memory Model Exam
Page 147 and 148:
Application Level Memory Model Exam
Page 149 and 150:
Page 151 and 152:
Application Level Memory Model Beha
Page 153 and 154:
whether it is suitable for executio
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A3.8 Memory access order Applicatio
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Synchronization primitives Applicat
Page 159 and 160:
A3.8.2 Ordering requirements for me
Page 161 and 162:
A3.8.3 Memory barriers Application
Page 163 and 164:
Page 165 and 166:
A3.9 Caches and memory hierarchy Ap
Page 167 and 168:
Data coherency issues You can ensur
Page 169 and 170:
Chapter A4 The Instruction Sets Thi
Page 171 and 172:
Note The Instruction Sets This perm
Page 173 and 174:
A4.2.2 Use of labels in UAL instruc
Page 175 and 176:
A4.3 Branch instructions The Instru
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The Instruction Sets These instruct
Page 179 and 180:
A4.4.3 Multiply instructions The In
Page 181 and 182:
A4.4.4 Saturating instructions The
Page 183 and 184:
A4.4.6 Miscellaneous data-processin
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A4.4.8 Divide instructions The Inst
Page 187 and 188:
A4.6 Load/store instructions The In
Page 189 and 190:
Note The Instruction Sets Not every
Page 191 and 192:
A4.8 Miscellaneous instructions The
Page 193 and 194:
A4.10 Coprocessor instructions The
Page 195 and 196:
A4.11.1 Element and structure load/
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A4.12 Advanced SIMD and VFP registe
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The Instruction Sets Figure A4-4 Ad
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A4.13.3 Advanced SIMD comparison in
Page 203 and 204:
A4.13.5 Advanced SIMD multiply inst
Page 205 and 206:
The Instruction Sets Table A4-21 Mi
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Chapter A5 ARM Instruction Set Enco
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A5.1.2 UNDEFINED and UNPREDICTABLE
Page 211 and 212:
A5.2.1 Data-processing (register) A
Page 213 and 214:
A5.2.2 Data-processing (register-sh
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A5.2.4 Modified immediate constants
Page 217 and 218:
ARM Instruction Set Encoding unrota
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ARM Instruction Set Encoding A5.2.6
Page 221 and 222:
A5.2.9 Extra load/store instruction
Page 223 and 224:
Page 225 and 226:
A5.3 Load/store word and unsigned b
Page 227 and 228:
A5.4 Media instructions Table A5-16
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A5.4.2 Parallel addition and subtra
Page 231 and 232:
ARM Instruction Set Encoding Table
Page 233 and 234:
A5.5 Branch, branch with link, and
Page 235 and 236:
10xxx1 1 not 101x - Move to ARM cor
Page 237 and 238:
Page 239 and 240:
Chapter A6 Thumb Instruction Set En
Page 241 and 242:
A6.1.2 Use of 0b1111 as a register
Page 243 and 244:
16-bit Thumb instruction support fo
Page 245 and 246:
A6.2.1 Shift (immediate), add, subt
Page 247 and 248:
A6.2.3 Special data instructions an
Page 249 and 250:
A6.2.5 Miscellaneous 16-bit instruc
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A6.2.6 Conditional branch, and Supe
Page 253 and 254:
Thumb Instruction Set Encoding A6.3
Page 255 and 256:
A6.3.2 Modified immediate constants
Page 257 and 258:
A6.3.3 Data-processing (plain binar
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Change Processor State, and hints T
Page 261 and 262:
Page 263 and 264:
A6.3.7 Load word Thumb Instruction
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op1 op2 Rn Rt Instruction See 00 1x
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op1 op2 Rn Rt Instruction See Thumb
Page 269 and 270:
Page 271 and 272:
A6.3.12 Data-processing (register)
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A6.3.13 Parallel addition and subtr
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A6.3.15 Miscellaneous operations Th
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A6.3.17 Long multiply, long multipl
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op1 op coproc Rn Instructions See T
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Chapter A7 Advanced SIMD and VFP In
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A7.2 Advanced SIMD and VFP instruct
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Syntax flexibility There is some fl
Page 287 and 288:
A7.2.5 Register lists Advanced SIMD
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A7.3.1 Advanced SIMD scalars Advanc
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U A B C See 0 1x11x - xxx0 Vector E
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A B U C Instruction See Advanced SI
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A7.4.2 Three registers of different
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A7.4.4 Two registers and a shift am
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A7.4.5 Two registers, miscellaneous
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A7.4.6 One register and a modified
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Operation // AdvSIMDExpandImm() //
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opc2 opc3 Instruction See - x0 Vect
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Advanced SIMD and VFP Instruction E
Page 309 and 310:
1 0x00 1000 Advanced SIMD and VFP I
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Advanced SIMD and VFP Instruction E
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Chapter A8 Instruction Details This
Page 315 and 316:
Each instruction encoding descripti
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Note Instruction Details The pre-UA
Page 319 and 320:
A8.2 Standard assembler syntax fiel
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A8.3.1 Pseudocode details of condit
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Encoding The assembler encodes int
Page 325 and 326:
A8.5 Memory accesses Commonly, the
Page 327 and 328:
Assembler syntax ADC{S} {,} , # whe
Page 329 and 330:
Assembler syntax ADC{S} {,} , {,}
Page 331 and 332:
Assembler syntax ADC{S} {,} , , w
Page 333 and 334:
Assembler syntax Instruction Detail
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Assembler syntax ADD{S} {,} , # whe
Page 337 and 338:
Assembler syntax ADD{S} {,} , {,}
Page 339 and 340:
Assembler syntax ADD{S} {,} , , w
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Assembler syntax ADD{S} {,} SP, # A
Page 343 and 344:
Assembler syntax ADD{S} {,} SP, {,
Page 345 and 346:
Assembler syntax ADR , Normal synt
Page 347 and 348:
Assembler syntax AND{S} {,} , # whe
Page 349 and 350:
Assembler syntax AND{S} {,} , {,}
Page 351 and 352:
Assembler syntax AND{S} {,} , , w
Page 353 and 354:
Assembler syntax ASR{S} {,} , # whe
Page 355 and 356:
Assembler syntax ASR{S} {,} , wher
Page 357 and 358:
Related encodings See Branches and
Page 359 and 360:
Assembler syntax BFC , #, # where:
Page 361 and 362:
Assembler syntax BFI , , #, # where
Page 363 and 364:
Assembler syntax BIC{S} {,} , # whe
Page 365 and 366:
Assembler syntax BIC{S} {,} , {,}
Page 367 and 368:
Assembler syntax BIC{S} {,} , , w
Page 369 and 370:
Assembler syntax BKPT # where: See
Page 371 and 372:
Assembler syntax BL{X} where: Inst
Page 373 and 374:
Assembler syntax BLX where: See S
Page 375 and 376:
Assembler syntax BX where: See St
Page 377 and 378:
Assembler syntax BXJ where: See S
Page 379 and 380:
Assembler syntax CB{N}Z , where: I
Page 381 and 382:
Assembler syntax CDP{2} , #, , , {
Page 383 and 384:
Assembler syntax CLREX where: Instr
Page 385 and 386:
Assembler syntax CLZ , where: See
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Assembler syntax CMN , # where: Se
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Assembler syntax CMN , {,} where:
Page 391 and 392:
Assembler syntax CMN , , where:
Page 393 and 394:
Assembler syntax CMP , # where: Se
Page 395 and 396:
Assembler syntax CMP , {,} where:
Page 397 and 398:
Assembler syntax CMP , , where:
Page 399 and 400:
Assembler syntax CPY , This is equ
Page 401 and 402:
Assembler syntax DBG # where: See
Page 403 and 404:
Operation Instruction Details OSH O
Page 405 and 406:
Operation Instruction Details OSH O
Page 407 and 408:
Assembler syntax EOR{S} {,} , # whe
Page 409 and 410:
Assembler syntax EOR{S} {,} , {,}
Page 411 and 412:
Assembler syntax EOR{S} {,} , , w
Page 413 and 414:
Former ARM assembler mnemonic FLDMX
Page 415 and 416:
Assembler syntax ISB {} where: Inst
Page 417 and 418:
Table A8-3 shows how the values of
Page 419 and 420:
Assembler syntax LDC{2}{L} ,,[{,#+/
Page 421 and 422:
Page 423 and 424:
Instruction Details The base regis
Page 425 and 426:
Assembler syntax LDMDA {!}, where:
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Instruction Details The SP can be i
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Assembler syntax LDMIB {!}, where:
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Assembler syntax LDR , [ {, #+/-}]
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Assembler syntax LDR , [ {, #+/-}]
Page 435 and 436:
Instruction Details The label of t
Page 437 and 438:
Assembler syntax LDR , [, +/-{, }]
Page 439 and 440:
Assembler syntax LDRB , [ {, #+/-}]
Page 441 and 442:
Assembler syntax LDRB , [ {, #+/-}]
Page 443 and 444:
Assembler syntax LDRB , Normal for
Page 445 and 446:
Assembler syntax LDRB , [, +/-{, }]
Page 447 and 448:
Assembler syntax LDRBT , [ {, #}] O
Page 449 and 450:
Assembler syntax LDRD , , [ {, #+/-
Page 451 and 452:
Assembler syntax LDRD , , Normal f
Page 453 and 454:
Assembler syntax LDRD , , [, +/-] O
Page 455 and 456:
Assembler syntax LDREX , [ {,#}] wh
Page 457 and 458:
Assembler syntax LDREXB , [] where:
Page 459 and 460:
Assembler syntax LDREXD , , [] wher
Page 461 and 462:
Assembler syntax LDREXH , [] where:
Page 463 and 464:
Assembler syntax LDRH , [ {, #+/-}]
Page 465 and 466:
Assembler syntax LDRH , [ {, #+/-}]
Page 467 and 468:
Assembler syntax LDRH , Normal for
Page 469 and 470:
Assembler syntax LDRH , [, {, LSL #
Page 471 and 472:
Assembler syntax LDRHT , [ {, #}] O
Page 473 and 474:
Assembler syntax LDRSB , [ {, #+/-}
Page 475 and 476:
Assembler syntax LDRSB , Normal fo
Page 477 and 478:
Assembler syntax LDRSB , [, {, LSL
Page 479 and 480:
Assembler syntax LDRSBT , [ {, #}]
Page 481 and 482:
Assembler syntax LDRSH , [ {, #+/-}
Page 483 and 484:
Assembler syntax LDRSH , Normal fo
Page 485 and 486:
Assembler syntax LDRSH , [, {, LSL
Page 487 and 488:
Assembler syntax LDRSHT , [ {, #}]
Page 489 and 490:
Assembler syntax LDRT , [ {, #}] Of
Page 491 and 492:
Assembler syntax LSL{S} {,} , # whe
Page 493 and 494:
Assembler syntax LSL{S} {,} , wher
Page 495 and 496:
Assembler syntax LSR{S} {,} , # whe
Page 497 and 498:
Assembler syntax LSR{S} {,} , wher
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Assembler syntax MCR{2} , #, , , {,
Page 501 and 502:
Assembler syntax MCRR{2} , #, , ,
Page 503 and 504:
Assembler syntax MLA{S} , , , wher
Page 505 and 506:
Assembler syntax MLS , , , where:
Page 507 and 508:
Assembler syntax MOV{S} , # All enc
Page 509 and 510:
See Standard assembler syntax field
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Assembler syntax Table A8-4 shows t
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Assembler syntax MOVT , # where: S
Page 515 and 516:
Assembler syntax MRC{2} , #, , , {,
Page 517 and 518:
Assembler syntax MRRC{2} , #, , ,
Page 519 and 520:
Assembler syntax MRS , where: See
Page 521 and 522:
Operation if ConditionPassed() then
Page 523 and 524:
Operation if ConditionPassed() then
Page 525 and 526:
Assembler syntax MUL{S} {,} , wher
Page 527 and 528:
Assembler syntax MVN{S} , # where:
Page 529 and 530:
Assembler syntax MVN{S} , {, } whe
Page 531 and 532:
Assembler syntax MVN{S} , , where
Page 533 and 534:
Assembler syntax NEG , This is equ
Page 535 and 536:
Assembler syntax NOP where: See St
Page 537 and 538:
Assembler syntax ORN{S} {,} , # whe
Page 539 and 540:
Assembler syntax ORN{S} {,} , {,}
Page 541 and 542:
Assembler syntax ORR{S} {,} , # whe
Page 543 and 544:
Assembler syntax ORR{S} {,} , {,}
Page 545 and 546:
Assembler syntax ORR{S} {,} , , w
Page 547 and 548:
Assembler syntax PKHBT {,} , {, LS
Page 549 and 550:
Assembler syntax PLD{W} [ {, #+/-}]
Page 551 and 552:
Assembler syntax PLD Normal form P
Page 553 and 554:
Assembler syntax PLD[W] [, +/- {, }
Page 555 and 556:
Assembler syntax where: Instruction
Page 557 and 558:
Assembler syntax PLI [, +/- {, }] w
Page 559 and 560:
Assembler syntax POP Standard synt
Page 561 and 562:
Assembler syntax PUSH Standard syn
Page 563 and 564:
Assembler syntax QADD {,} , where:
Page 565 and 566:
Assembler syntax QADD16 {,} , wher
Page 567 and 568:
Assembler syntax QADD8 {,} , where
Page 569 and 570:
Assembler syntax QASX {,} , where:
Page 571 and 572:
Assembler syntax QDADD {,} , where
Page 573 and 574:
Assembler syntax QDSUB {,} , where
Page 575 and 576:
Assembler syntax QSAX {,} , where:
Page 577 and 578:
Assembler syntax QSUB {,} , where:
Page 579 and 580:
Assembler syntax QSUB16 {,} , wher
Page 581 and 582:
Assembler syntax QSUB8 {,} , where
Page 583 and 584:
Assembler syntax RBIT , where: Se
Page 585 and 586:
Assembler syntax REV , where: See
Page 587 and 588:
Assembler syntax REV16 , where: S
Page 589 and 590:
Assembler syntax REVSH , where: S
Page 591 and 592:
Assembler syntax ROR{S} {,} , # whe
Page 593 and 594:
Assembler syntax ROR{S} {,} , wher
Page 595 and 596:
Assembler syntax RRX{S} {,} where:
Page 597 and 598:
Assembler syntax RSB{S} {,} , # whe
Page 599 and 600:
Assembler syntax RSB{S} {,} , {,}
Page 601 and 602:
Assembler syntax RSB{S} {,} , , w
Page 603 and 604:
Assembler syntax RSC{S} {,} , # whe
Page 605 and 606:
Assembler syntax RSC{S} {,} , {,}
Page 607 and 608:
Assembler syntax RSC{S} {,} , , w
Page 609 and 610:
Assembler syntax SADD16 {,} , wher
Page 611 and 612:
Assembler syntax SADD8 {,} , where
Page 613 and 614:
Assembler syntax SASX {,} , where:
Page 615 and 616:
Assembler syntax SBC{S} {,} , # whe
Page 617 and 618:
Assembler syntax SBC{S} {,} , {,}
Page 619 and 620:
Assembler syntax SBC{S} {,} , , w
Page 621 and 622:
Assembler syntax SBFX , , #, # wher
Page 623 and 624:
Assembler syntax SDIV {,} , where:
Page 625 and 626:
Assembler syntax SEL {,} , where:
Page 627 and 628:
Assembler syntax SETEND where: Se
Page 629 and 630:
Assembler syntax SEV where: See St
Page 631 and 632:
Assembler syntax SHADD16 {,} , whe
Page 633 and 634:
Assembler syntax SHADD8 {,} , wher
Page 635 and 636:
Assembler syntax SHASX {,} , where
Page 637 and 638:
Assembler syntax SHSAX {,} , where
Page 639 and 640:
Assembler syntax SHSUB16 {,} , whe
Page 641 and 642:
Assembler syntax SHSUB8 {,} , wher
Page 643 and 644:
Assembler syntax SMLA , , , where:
Page 645 and 646:
Assembler syntax SMLAD{X} , , , wh
Page 647 and 648:
Assembler syntax SMLAL{S} , , , wh
Page 649 and 650:
Assembler syntax SMLAL , , , where
Page 651 and 652:
Assembler syntax SMLALD{X} , , , w
Page 653 and 654:
Assembler syntax SMLAW , , , where
Page 655 and 656:
Assembler syntax SMLSD{X} , , , wh
Page 657 and 658:
Assembler syntax SMLSLD{X} , , , w
Page 659 and 660:
Assembler syntax SMMLA{R} , , , wh
Page 661 and 662:
Assembler syntax SMMLS{R} , , , wh
Page 663 and 664:
Assembler syntax SMMUL{R} {,} , wh
Page 665 and 666:
Assembler syntax SMUAD{x} {,} , wh
Page 667 and 668:
Assembler syntax SMUL {,} , where:
Page 669 and 670:
Assembler syntax SMULL{S} , , , wh
Page 671 and 672:
Assembler syntax SMULW {,} , where
Page 673 and 674:
Assembler syntax SMUSD{X} {,} , wh
Page 675 and 676:
Assembler syntax SSAT , #, {,} whe
Page 677 and 678:
Assembler syntax SSAT16 , #, where
Page 679 and 680:
Assembler syntax SSAX {,} , where:
Page 681 and 682:
Assembler syntax SSUB16 {,} , wher
Page 683 and 684:
Assembler syntax SSUB8 {,} , where
Page 685 and 686:
Assembler syntax STC{2}{L} ,,[{,#+/
Page 687 and 688:
Instruction Details Is a list of o
Page 689 and 690:
Assembler syntax STMDA {!}, where:
Page 691 and 692:
Instruction Details The SP and PC c
Page 693 and 694:
Assembler syntax STMIB {!}, where:
Page 695 and 696:
Assembler syntax STR , [ {, #+/-}]
Page 697 and 698:
Assembler syntax STR , [ {, #+/-}]
Page 699 and 700:
Assembler syntax STR , [, {, }] Off
Page 701 and 702:
Assembler syntax STRB , [ {, #+/-}]
Page 703 and 704:
Assembler syntax STRB , [ {, #+/-}]
Page 705 and 706:
Assembler syntax STRB , [, {, }] Of
Page 707 and 708:
Assembler syntax STRBT , [ {, #}] O
Page 709 and 710:
Assembler syntax STRD , , [ {, #+/-
Page 711 and 712:
Assembler syntax STRD , , [, +/-] O
Page 713 and 714:
Assembler syntax STREX , , [ {,#}]
Page 715 and 716:
Assembler syntax STREXB , , [] wher
Page 717 and 718:
Assembler syntax STREXD , , , [] wh
Page 719 and 720:
Assembler syntax STREXH , , [] wher
Page 721 and 722:
Assembler syntax STRH , [ {, #+/-}]
Page 723 and 724:
Assembler syntax STRH , [ {, #+/-}]
Page 725 and 726:
Assembler syntax STRH , [, +/-{, LS
Page 727 and 728:
Assembler syntax STRHT , [ {, #}] O
Page 729 and 730:
Assembler syntax STRT , [ {, #}] Of
Page 731 and 732:
Page 733 and 734:
Assembler syntax SUB{S} {,} , # whe
Page 735 and 736:
Assembler syntax SUB{S} {,} , {,}
Page 737 and 738:
Assembler syntax SUB{S} {,} , , w
Page 739 and 740:
Page 741 and 742:
Assembler syntax SUB{S} {,} SP, {,
Page 743 and 744:
Assembler syntax SVC # where: See
Page 745 and 746:
Assembler syntax SWP{B} , , [] wher
Page 747 and 748:
Assembler syntax SXTAB {,} , {, }
Page 749 and 750:
Assembler syntax SXTAB16 {,} , {,
Page 751 and 752:
Assembler syntax SXTAH {,} , {, }
Page 753 and 754:
Assembler syntax SXTB {,} {, } whe
Page 755 and 756:
Assembler syntax SXTB16 {,} {, } w
Page 757 and 758:
Assembler syntax SXTH {,} {, } whe
Page 759 and 760:
Assembler syntax TBB [, ] TBH [, ,
Page 761 and 762:
Assembler syntax TEQ , # where: Se
Page 763 and 764:
Assembler syntax TEQ , {,} where:
Page 765 and 766:
Assembler syntax TEQ , , where:
Page 767 and 768:
Assembler syntax TST , # where: Se
Page 769 and 770:
Assembler syntax TST , {,} where:
Page 771 and 772:
Assembler syntax TST , , where:
Page 773 and 774:
Assembler syntax UADD16 {,} , wher
Page 775 and 776:
Assembler syntax UADD8 {,} , where
Page 777 and 778:
Assembler syntax UASX {,} , where:
Page 779 and 780:
Assembler syntax UBFX , , #, # wher
Page 781 and 782:
Assembler syntax UDIV {,} , where:
Page 783 and 784:
Assembler syntax UHADD16 {,} , whe
Page 785 and 786:
Assembler syntax UHADD8 {,} , wher
Page 787 and 788:
Assembler syntax UHASX {,} , where
Page 789 and 790:
Assembler syntax UHSAX {,} , where
Page 791 and 792:
Assembler syntax UHSUB16 {,} , whe
Page 793 and 794:
Assembler syntax UHSUB8 {,} , wher
Page 795 and 796:
Assembler syntax UMAAL , , , where
Page 797 and 798:
Assembler syntax UMLAL{S} , , , wh
Page 799 and 800:
Assembler syntax UMULL{S} , , , wh
Page 801 and 802:
Assembler syntax UQADD16 {,} , whe
Page 803 and 804:
Assembler syntax UQADD8 {,} , wher
Page 805 and 806:
Assembler syntax UQASX {,} , where
Page 807 and 808:
Assembler syntax UQSAX {,} , where
Page 809 and 810:
Assembler syntax UQSUB16 {,} , whe
Page 811 and 812:
Assembler syntax UQSUB8 {,} , wher
Page 813 and 814:
Assembler syntax USAD8 {,} , where
Page 815 and 816:
Assembler syntax USADA8 , , , wher
Page 817 and 818:
Assembler syntax USAT , #, {,} whe
Page 819 and 820:
Assembler syntax USAT16 , #, where
Page 821 and 822:
Assembler syntax USAX {,} , where:
Page 823 and 824:
Assembler syntax USUB16 {,} , wher
Page 825 and 826:
Assembler syntax USUB8 {,} , where
Page 827 and 828:
Assembler syntax UXTAB {,} , {, }
Page 829 and 830:
Assembler syntax UXTAB16 {,} , {,
Page 831 and 832:
Assembler syntax UXTAH {,} , {, }
Page 833 and 834:
Assembler syntax UXTB {,} {, } whe
Page 835 and 836:
Assembler syntax UXTB16 {,} {, } w
Page 837 and 838:
Assembler syntax UXTH {,} {, } whe
Page 839 and 840:
Page 841 and 842:
Page 843 and 844:
Page 845 and 846:
Page 847 and 848:
Assembler syntax V.F32 {,} , Encod
Page 849 and 850:
Assembler syntax VADD. {,} , VADD.
Page 851 and 852:
Page 853 and 854:
Assembler syntax VADDHN. , , where
Page 855 and 856:
Assembler syntax VADDL. , , Encode
Page 857 and 858:
Assembler syntax VAND{.} {,} , Enc
Page 859 and 860:
Assembler syntax VBIC. {,} , # Enco
Page 861 and 862:
Assembler syntax VBIC{.} {,} , Enc
Page 863 and 864:
Assembler syntax V{.} {,} , Encode
Page 865 and 866:
Assembler syntax VCEQ. {,} , Encod
Page 867 and 868:
Assembler syntax VCEQ. {,} , #0 Enc
Page 869 and 870:
Assembler syntax VCGE. {,} , Encod
Page 871 and 872:
Assembler syntax VCGE. {,} , #0 Enc
Page 873 and 874:
Assembler syntax VCGT. {,} , Encod
Page 875 and 876:
Assembler syntax VCGT. {,} , #0 Enc
Page 877 and 878:
Assembler syntax VCLE. {,} , #0 Enc
Page 879 and 880:
Assembler syntax VCLS. , Encoded a
Page 881 and 882:
Assembler syntax VCLT. {,} , #0 Enc
Page 883 and 884:
Assembler syntax VCLZ. , Encoded a
Page 885 and 886:
Page 887 and 888:
Assembler syntax VCNT.8 , Encoded
Page 889 and 890:
Assembler syntax VCVT.. , Encoded
Page 891 and 892:
Assembler syntax VCVT{R}.S32.F64 ,
Page 893 and 894:
Assembler syntax VCVT.. , , # Encod
Page 895 and 896:
Assembler syntax VCVT..F64 , ,# op
Page 897 and 898:
Assembler syntax VCVT.F64.F32 , En
Page 899 and 900:
Page 901 and 902:
Page 903 and 904:
Assembler syntax VDIV.F64 {,} , En
Page 905 and 906:
Assembler syntax VDUP. , Encoded a
Page 907 and 908:
Assembler syntax VDUP. , Encoded a
Page 909 and 910:
Assembler syntax VEOR{.} {,} , Enc
Page 911 and 912:
Assembler syntax VEXT. {,} , , # En
Page 913 and 914:
Assembler syntax VH. {,} , Encoded
Page 915 and 916:
32 encoded as size = 0b10 64 encode
Page 917 and 918:
Instruction Details The register c
Page 919 and 920:
Assembler syntax VLD1. , [{@}] Rm =
Page 921 and 922:
32 encoded as size = 0b10. The lis
Page 923 and 924:
Instruction Details The registers
Page 925 and 926:
Instruction Details 64 8-byte align
Page 927 and 928:
The list of registers to load. It m
Page 929 and 930:
Page 931 and 932:
Contains an address offset applied
Page 933 and 934:
The list of registers to load. It m
Page 935 and 936:
Page 937 and 938:
{, , , } The base address for the
Page 939 and 940:
Assembler syntax VLDM{}{.} {!}, wh
Page 941 and 942:
The destination register for a doub
Page 943 and 944:
Assembler syntax V. {,} , Encoded
Page 945 and 946:
Assembler syntax V.F32 {,} , Encod
Page 947 and 948:
Assembler syntax where: Must be ei
Page 949 and 950:
Page 951 and 952:
Assembler syntax where: Must be ei
Page 953 and 954:
Page 955 and 956:
Page 957 and 958:
Assembler syntax VMOV{.} , where:
Page 959 and 960:
Assembler syntax VMOV{.} , where:
Page 961 and 962:
Assembler syntax VMOV , Encoded as
Page 963 and 964:
Assembler syntax VMOV , , , Encode
Page 965 and 966:
Assembler syntax VMOV , , Encoded
Page 967 and 968:
Assembler syntax VMOVL.dt> , where
Page 969 and 970:
Assembler syntax VMOVN. , where: I
Page 971 and 972:
Assembler syntax VMRS , FPSCR where
Page 973 and 974:
Assembler syntax VMSR FPSCR, where
Page 975 and 976:
Page 977 and 978:
Page 979 and 980:
Page 981 and 982:
Page 983 and 984:
Assembler syntax VMVN{.} , VMVN{.}
Page 985 and 986:
Page 987 and 988:
Assembler syntax where: See Standa
Page 989 and 990:
Assembler syntax VORN{.} {,} , Enc
Page 991 and 992:
Assembler syntax VORR. {,} , # Enco
Page 993 and 994:
Assembler syntax VORR{.} {,} , Enc
Page 995 and 996:
Assembler syntax VPADAL. , Encoded
Page 997 and 998:
Assembler syntax VPADD. {,} , Enco
Page 999 and 1000:
Page 1001 and 1002:
Assembler syntax VPADDL. , Encoded
Page 1003 and 1004:
Assembler syntax VP. {,} , Encoded
Page 1005 and 1006:
Page 1007 and 1008:
Assembler syntax VPOP{.} where: S
Page 1009 and 1010:
Assembler syntax VPUSH{.} where:
Page 1011 and 1012:
Assembler syntax VQABS. , Encoded
Page 1013 and 1014:
Assembler syntax VQADD. {,} , Enco
Page 1015 and 1016:
Assembler syntax VQD. , , VQD. , ,
Page 1017 and 1018:
Page 1019 and 1020:
Assembler syntax VQDMULL. , , VQDM
Page 1021 and 1022:
Assembler syntax VQMOV{U}N. , wher
Page 1023 and 1024:
Assembler syntax VQNEG. , Encoded
Page 1025 and 1026:
Page 1027 and 1028:
Assembler syntax VQRSHL. {,} , Enc
Page 1029 and 1030:
Assembler syntax VQRSHR{U}N. , , #
Page 1031 and 1032:
Assembler syntax VQSHL. {,} , Enco
Page 1033 and 1034:
Assembler syntax VQSHL{U}. {,} , #
Page 1035 and 1036:
Assembler syntax VQSHR{U}N. , , # w
Page 1037 and 1038:
Assembler syntax VQSUB. {,} , Enco
Page 1039 and 1040:
Assembler syntax VRADDHN. , , wher
Page 1041 and 1042:
Assembler syntax VRECPE. , Encoded
Page 1043 and 1044:
Assembler syntax VRECPS.F32 {,} ,
Page 1045 and 1046:
Assembler syntax VREV. , Encoded a
Page 1047 and 1048:
Assembler syntax VRHADD. {,} , Enc
Page 1049 and 1050:
Assembler syntax VRSHL. {,} , Enco
Page 1051 and 1052:
Assembler syntax VRSHR. {,} , # Enc
Page 1053 and 1054:
Assembler syntax VRSHRN.I , , # whe
Page 1055 and 1056:
Assembler syntax VRSQRTE. , Encode
Page 1057 and 1058:
Page 1059 and 1060:
Assembler syntax VRSRA. {,} , # Enc
Page 1061 and 1062:
Assembler syntax VRSUBHN. , , wher
Page 1063 and 1064:
Assembler syntax VSHL.I {,} , # Enc
Page 1065 and 1066:
Assembler syntax VSHL. {,} , Encod
Page 1067 and 1068:
Assembler syntax VSHLL. , , # where
Page 1069 and 1070:
Assembler syntax VSHR. {,} , # Enco
Page 1071 and 1072:
Assembler syntax VSHRN.I , , # wher
Page 1073 and 1074:
Assembler syntax VSLI. {,} , # Enco
Page 1075 and 1076:
Assembler syntax VSQRT.F64 , Encod
Page 1077 and 1078:
Assembler syntax VSRA. {,} , # Enco
Page 1079 and 1080:
Assembler syntax VSRI. {,} , # Enco
Page 1081 and 1082:
32 encoded as size = 0b10 64 encode
Page 1083 and 1084:
Instruction Details The register c
Page 1085 and 1086:
32 encoded as size = 0b10. The lis
Page 1087 and 1088:
Page 1089 and 1090:
The list of registers to store. It
Page 1091 and 1092:
Page 1093 and 1094:
The list of registers to store. It
Page 1095 and 1096:
Page 1097 and 1098:
Assembler syntax VSTM{}{.} {!}, wh
Page 1099 and 1100:
Assembler syntax VSTR{.64} , [{, #+
Page 1101 and 1102:
Assembler syntax VSUB. {,} , VSUB.
Page 1103 and 1104:
Page 1105 and 1106:
Assembler syntax VSUBHN. , , where
Page 1107 and 1108:
Assembler syntax VSUBL. , , Encode
Page 1109 and 1110:
Page 1111 and 1112:
Assembler syntax V.8 , , where: S
Page 1113 and 1114:
Assembler syntax VTRN. , Encoded a
Page 1115 and 1116:
Assembler syntax VTST. {,} , Encod
Page 1117 and 1118:
Assembler syntax VUZP. , Encoded a
Page 1119 and 1120:
Assembler syntax VZIP. , Encoded a
Page 1121 and 1122:
Assembler syntax WFE where: See St
Page 1123 and 1124:
Assembler syntax WFI where: See St
Page 1125 and 1126:
Assembler syntax YIELD where: See
Page 1127 and 1128:
Chapter A9 ThumbEE This chapter con
Page 1129 and 1130:
A9.1.2 Null checking ThumbEE A null
Page 1131 and 1132:
A9.1.4 IT block and check handlers
Page 1133 and 1134:
A9.3 Additional instructions in Thu
Page 1135 and 1136:
A9.4.1 LDR (register) ThumbEE Load
Page 1137 and 1138:
A9.4.3 LDRSH (register) ThumbEE Loa
Page 1139 and 1140:
A9.4.5 STRH (register) ThumbEE Stor
Page 1141 and 1142:
A9.5.1 CHKA ThumbEE CHKA (Check Arr
Page 1143 and 1144:
A9.5.3 HBLP ThumbEE HBLP (Handler B
Page 1145 and 1146:
A9.5.5 LDR (immediate) Load Registe
Page 1147 and 1148:
A9.5.6 STR (immediate) ThumbEE Stor
Page 1149:
Part B System Level Architecture
Page 1152 and 1153:
The System Level Programmers’ Mod
Page 1154 and 1155:
Page 1156 and 1157:
Page 1158 and 1159:
Page 1160 and 1161:
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Common Memory System Architecture F
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Virtual Memory System Architecture
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Protected Memory System Architectur
Page 1440 and 1441:
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Page 1520 and 1521:
The CPUID Identification Scheme B5.
Page 1522 and 1523:
Page 1524 and 1525:
The CPUID Identification Scheme Pro
Page 1526 and 1527:
The CPUID Identification Scheme Acc
Page 1528 and 1529:
The CPUID Identification Scheme TCM
Page 1530 and 1531:
The CPUID Identification Scheme L1
Page 1532 and 1533:
The CPUID Identification Scheme 0b0
Page 1534 and 1535:
The CPUID Identification Scheme L1
Page 1536 and 1537:
Page 1538 and 1539:
The CPUID Identification Scheme Ins
Page 1540 and 1541:
The CPUID Identification Scheme Sum
Page 1542 and 1543:
The CPUID Identification Scheme c0,
Page 1544 and 1545:
Page 1546 and 1547:
The CPUID Identification Scheme Mul
Page 1548 and 1549:
The CPUID Identification Scheme Syn
Page 1550 and 1551:
The CPUID Identification Scheme Bar
Page 1552 and 1553:
Page 1554 and 1555:
The CPUID Identification Scheme Rev
Page 1556 and 1557:
The CPUID Identification Scheme Sin
Page 1558 and 1559:
The CPUID Identification Scheme FtZ
Page 1560 and 1561:
System Instructions B6.1 Alphabetic
Page 1562 and 1563:
System Instructions If is specifie
Page 1564 and 1565:
System Instructions Is a list of o
Page 1566 and 1567:
System Instructions The pre-UAL syn
Page 1568 and 1569:
System Instructions B6.1.5 MRS Move
Page 1570 and 1571:
System Instructions B6.1.6 MSR (imm
Page 1572 and 1573:
System Instructions B6.1.7 MSR (reg
Page 1574 and 1575:
System Instructions B6.1.8 RFE Retu
Page 1576 and 1577:
System Instructions B6.1.9 SMC (pre
Page 1578 and 1579:
System Instructions B6.1.10 SRS Sto
Page 1580 and 1581:
System Instructions B6.1.11 STM (us
Page 1582 and 1583:
System Instructions B6.1.12 STRBT,
Page 1584 and 1585:
System Instructions The operation.
Page 1586 and 1587:
System Instructions Assembler synta
Page 1588 and 1589:
System Instructions Assembler synta
Page 1591 and 1592:
Chapter C1 Introduction to the ARM
Page 1593 and 1594:
C1.2 About the ARM Debug architectu
Page 1595 and 1596:
C1.2.2 Non-invasive debug Introduct
Page 1597 and 1598:
Introduction to the ARM Debug Archi
Page 1599 and 1600:
C1.4 Register interfaces Introducti
Page 1601 and 1602:
Chapter C2 Invasive Debug Authentic
Page 1603 and 1604:
in Non-secure state and also in Sec
Page 1605 and 1606:
Chapter C3 Debug Events This chapte
Page 1607 and 1608:
BKPT Instruction Breakpoint Vector
Page 1609 and 1610:
C3.2 Software debug events A Softwa
Page 1611 and 1612:
Debug event generation conditions d
Page 1613 and 1614:
Condition for breakpoint generation
Page 1615 and 1616:
IVA mismatch with an address range
Page 1617 and 1618:
Note Debug Events When programming
Page 1619 and 1620:
Note Instructions that branch to th
Page 1621 and 1622:
Debug Events For each of the memory
Page 1623 and 1624:
Debug Events For example, if the se
Page 1625 and 1626:
Debug Events One set for exceptions
Page 1627 and 1628:
If the Security Extensions are impl
Page 1629 and 1630:
Debug Events When Monitor debug-mod
Page 1631 and 1632:
Debug Events 2. The processor takes
Page 1633 and 1634:
Each unit of the instruction is che
Page 1635 and 1636:
BVR_match = byte_select_match && (c
Page 1637 and 1638:
eturn; VCR_Recent_IRQ_NS_Valid = TR
Page 1639 and 1640:
When Monitor debug-mode is configur
Page 1641 and 1642:
when ‘10’ secure_state_match =
Page 1643 and 1644:
In v6 Debug and v6.1 Debug: Debug E
Page 1645 and 1646:
Debug Events Usually, exception ret
Page 1647 and 1648:
C3.5 Debug event prioritization Deb
Page 1649 and 1650:
Chapter C4 Debug Exceptions This ch
Page 1651 and 1652:
C4.1.2 Debug exception on Watchpoin
Page 1653 and 1654:
Debug Exceptions In Monitor debug-m
Page 1655 and 1656:
Chapter C5 Debug State This chapter
Page 1657 and 1658:
C5.2 Entering Debug state Debug Sta
Page 1659 and 1660:
C5.2.2 Asynchronous aborts and entr
Page 1661 and 1662:
C5.3 Behavior of the PC and CPSR in
Page 1663 and 1664:
C5.4 Executing instructions in Debu
Page 1665 and 1666:
Note Table C5-2 on page C5-10 does
Page 1667 and 1668:
C5.5 Privilege in Debug state Debug
Page 1669 and 1670:
Being in Debug state when invasive
Page 1671 and 1672:
Instructions for CP14 and CP15 Debu
Page 1673 and 1674:
C5.6 Behavior of non-invasive debug
Page 1675 and 1676:
Undefined Instruction Debug State U
Page 1677 and 1678:
Debug State C5.7.1 Undefined Instru
Page 1679 and 1680:
C5.8.1 Access to specific cache man
Page 1681 and 1682:
C5.8.2 Debug state Cache and MMU Co
Page 1683 and 1684:
Note Leaving Debug state is not a m
Page 1685 and 1686:
Chapter C6 Debug Register Interface
Page 1687 and 1688:
Debug Register Interfaces The Debug
Page 1689 and 1690:
Debug Register Interfaces The proto
Page 1691 and 1692:
OS Save and Restore registers, and
Page 1693 and 1694:
The OS Save and Restore mechanism i
Page 1695 and 1696:
The DCC status flags themselves:
Page 1697 and 1698:
CMP R1, #0 ; Check for zero SaveDeb
Page 1699 and 1700:
Debug Register Interfaces Example C
Page 1701 and 1702:
Table C6-1 summarizes the v7 Debug
Page 1703 and 1704:
Register number 33 0x084 Write-only
Page 1705 and 1706:
Register number C6.3.1 Internal and
Page 1707 and 1708:
C6.3.2 Effect of the Security Exten
Page 1709 and 1710:
Debug Register Interfaces Synchroni
Page 1711 and 1712:
Note Debug Register Interfaces The
Page 1713 and 1714:
Debug Register Interfaces Access to
Page 1715 and 1716:
Debug Register Interfaces When the
Page 1717 and 1718:
MRC p14,0,,c0,c5,0 STC p14,c5, MCR
Page 1719 and 1720:
Debug Register Interfaces Accesses
Page 1721 and 1722:
Note The Baseline CP14 instructions
Page 1723 and 1724:
Debug Register Interfaces v7 Debug
Page 1725 and 1726:
Debug Register Interfaces When the
Page 1727 and 1728:
Debug Register Interfaces C6.7 The
Page 1729 and 1730:
Debug Register Interfaces bits [23:
Page 1731 and 1732:
Access permissions for the external
Page 1733 and 1734:
Debug Register Interfaces Table C6-
Page 1735 and 1736:
Debug Register Interfaces C6.7.5 Re
Page 1737 and 1738:
Chapter C7 Non-invasive Debug Authe
Page 1739 and 1740:
Non-invasive Debug Authentication T
Page 1741 and 1742:
Page 1743 and 1744:
C7.3.2 Trace All instructions and d
Page 1745 and 1746:
Page 1747 and 1748:
Chapter C8 Sample-based Profiling T
Page 1749 and 1750:
Note ARM recommends that an impleme
Page 1751 and 1752:
Chapter C9 Performance Monitors Thi
Page 1753 and 1754:
The set of events that might be mon
Page 1755 and 1756:
C9.3 Accuracy of the performance mo
Page 1757 and 1758:
C9.5 Interaction with Security Exte
Page 1759 and 1760:
C9.7 Interaction with power saving
Page 1761 and 1762:
MRC p15,0,,c9,c12,4 UNPREDICTABLE.
Page 1763 and 1764:
C9.10 Event numbers The event numbe
Page 1765 and 1766:
Performance Monitors 0x0B Instructi
Page 1767 and 1768:
Transaction counts on external buse
Page 1769 and 1770:
Chapter C10 Debug Registers Referen
Page 1771 and 1772:
C10.2 Debug identification register
Page 1773 and 1774:
nSUHD_imp, bit [14] Debug Registers
Page 1775 and 1776:
Debug Registers Reference 0b0010 DB
Page 1777 and 1778:
Debug Registers Reference One imple
Page 1779 and 1780:
In v7 Debug, the format of the DBGD
Page 1781 and 1782:
Debug Registers Reference On a read
Page 1783 and 1784:
Debug Registers Reference If the ex
Page 1785 and 1786:
Debug Registers Reference If a debu
Page 1787 and 1788:
SDABORT_l, bit [6] Debug Registers
Page 1789 and 1790:
Debug Registers Reference Table C10
Page 1791 and 1792:
Debug Registers Reference Debuggers
Page 1793 and 1794:
Stalling of accesses to the DCC reg
Page 1795 and 1796:
Debug Registers Reference When debu
Page 1797 and 1798:
C10.3.3 Debug Run Control Register
Page 1799 and 1800:
Debug state entry is the acknowledg
Page 1801 and 1802:
Note Debug Registers Reference When
Page 1803 and 1804:
Debug Registers Reference When the
Page 1805 and 1806:
Reset state Debug Registers Referen
Page 1807 and 1808:
Meaning of PC Sample Value, bits [1
Page 1809 and 1810:
Debug Registers Reference v7 Debug
Page 1811 and 1812:
C10.4.2 Target to Host Data Transfe
Page 1813 and 1814:
Access mode a Debug Registers Refer
Page 1815 and 1816:
Access mode a Non- blocking Flag b
Page 1817 and 1818:
When used for IVA comparison the fo
Page 1819 and 1820:
Debug Registers Reference Bit [21],
Page 1821 and 1822:
Debug Registers Reference 0b101 Lin
Page 1823 and 1824:
Breakpoint enable, bit [0] 0b11 Mat
Page 1825 and 1826:
Page 1827 and 1828:
Linked comparisons Debug Registers
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C10.5.4 Watchpoint Control Register
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0b01 watchpoint generated on match
Page 1833 and 1834:
Byte address masking behavior on DV
Page 1835 and 1836:
Note Debug Registers Reference This
Page 1837 and 1838:
31 30 29 28 27 26 25 24 16 15 14 13
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Vector catch operation when Securit
Page 1841 and 1842:
Page 1843 and 1844:
C10.6 OS Save and Restore registers
Page 1845 and 1846:
Locked, bit [1] Debug Registers Ref
Page 1847 and 1848:
The format of the DBGECR is: Bits [
Page 1849 and 1850:
C10.7.1 Debug State Cache Control R
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Permitted IMPLEMENTATION DEFINED li
Page 1853 and 1854:
Debug Registers Reference It is IMP
Page 1855 and 1856:
Permitted IMPLEMENTATION DEFINED li
Page 1857 and 1858:
Register number Access a Debug Regi
Page 1859 and 1860:
C10.8.2 Integration Mode Control Re
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C10.8.4 Claim Tag Clear Register (D
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C10.8.6 Lock Status Register (DBGLS
Page 1865 and 1866:
Non-secure invasive debug features
Page 1867 and 1868:
Note Debug Registers Reference ARMv
Page 1869 and 1870:
Revision 4 bits Revision number for
Page 1871 and 1872:
occupy the last four words of the 4
Page 1873 and 1874:
C10.9 Performance monitor registers
Page 1875 and 1876:
Debug Registers Reference X, bit [4
Page 1877 and 1878:
Table C10-25 shows the behavior of
Page 1879 and 1880:
Debug Registers Reference The forma
Page 1881 and 1882:
C10.9.6 c9, Event Counter Selection
Page 1883 and 1884:
C10.9.8 c9, Event Type Select Regis
Page 1885 and 1886:
C10.9.10 c9, User Enable Register (
Page 1887 and 1888:
Table C10-28 shows the behavior of
Page 1889:
Part D Appendices
Page 1892 and 1893:
Recommended External Debug Interfac
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Page 1896 and 1897:
Page 1898 and 1899:
Page 1900 and 1901:
Page 1902 and 1903:
Page 1904 and 1905:
Page 1906 and 1907:
Page 1908 and 1909:
Common VFP Subarchitecture Specific
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Page 1920 and 1921:
Page 1922 and 1923:
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Page 1926 and 1927:
Page 1928 and 1929:
Page 1930 and 1931:
Page 1932 and 1933:
Legacy Instruction Mnemonics C.1 Th
Page 1934 and 1935:
Legacy Instruction Mnemonics AppxC-
Page 1936 and 1937:
Deprecated and Obsolete Features D.
Page 1938 and 1939:
Page 1940 and 1941:
Page 1942 and 1943:
Page 1944 and 1945:
Page 1946 and 1947:
Fast Context Switch Extension (FCSE
Page 1948 and 1949:
Page 1950 and 1951:
Page 1952 and 1953:
VFP Vector Operation Support F.1 Ab
Page 1954 and 1955:
VFP Vector Operation Support Table
Page 1956 and 1957:
VFP Vector Operation Support Scalar
Page 1958 and 1959:
VFP Vector Operation Support AppxF-
Page 1960 and 1961:
ARMv6 Differences G.1 Introduction
Page 1962 and 1963:
ARMv6 Differences ARMv6T2 supports
Page 1964 and 1965:
ARMv6 Differences G.3 Application l
Page 1966 and 1967:
ARMv6 Differences G.3.3 Semaphore s
Page 1968 and 1969:
ARMv6 Differences G.4 Instruction s
Page 1970 and 1971:
ARMv6 Differences Table G-2 ARM ins
Page 1972 and 1973:
ARMv6 Differences G.4.2 Thumb instr
Page 1974 and 1975:
ARMv6 Differences G.5 System level
Page 1976 and 1977:
ARMv6 Differences G.5.2 The excepti
Page 1978 and 1979:
ARMv6 Differences G.6 System level
Page 1980 and 1981:
ARMv6 Differences ARMv6 defines a s
Page 1982 and 1983:
ARMv6 Differences TCM CP15 configur
Page 1984 and 1985:
ARMv6 Differences VMSAv6 translatio
Page 1986 and 1987:
ARMv6 Differences TCM access suppor
Page 1988 and 1989:
ARMv6 Differences CRn opc1 CRm opc2
Page 1990 and 1991:
ARMv6 Differences G.7.3 c0, ID supp
Page 1992 and 1993:
ARMv6 Differences When nU == 0 this
Page 1994 and 1995:
ARMv6 Differences Bit [17], TL TLB
Page 1996 and 1997:
ARMv6 Differences G.7.10 c7, Cache
Page 1998 and 1999:
ARMv6 Differences Accessing the Cac
Page 2000 and 2001:
ARMv6 Differences Blocking and non-
Page 2002 and 2003:
ARMv6 Differences R, bit [0] Block
Page 2004 and 2005:
ARMv6 Differences G.7.15 c9, TCM su
Page 2006 and 2007:
ARMv6 Differences Note Bit [1] was
Page 2008 and 2009:
ARMv6 Differences when the Security
Page 2010 and 2011:
ARMv6 Differences The format of a T
Page 2012 and 2013:
ARMv6 Differences For ARMv6, TLB lo
Page 2014 and 2015:
ARMv4 and ARMv5 Differences H.1 Int
Page 2016 and 2017:
ARMv4 and ARMv5 Differences H.2 App
Page 2018 and 2019:
ARMv4 and ARMv5 Differences H.3 App
Page 2020 and 2021:
ARMv4 and ARMv5 Differences Note Ta
Page 2022 and 2023:
ARMv4 and ARMv5 Differences H.3.4 M
Page 2024 and 2025:
ARMv4 and ARMv5 Differences H.4.1 A
Page 2026 and 2027:
ARMv4 and ARMv5 Differences Table H
Page 2028 and 2029:
ARMv4 and ARMv5 Differences Table H
Page 2030 and 2031:
ARMv4 and ARMv5 Differences H.5 Sys
Page 2032 and 2033:
ARMv4 and ARMv5 Differences The ARM
Page 2034 and 2035:
ARMv4 and ARMv5 Differences The Fas
Page 2036 and 2037:
ARMv4 and ARMv5 Differences First l
Page 2038 and 2039:
ARMv4 and ARMv5 Differences Second
Page 2040 and 2041:
ARMv4 and ARMv5 Differences H.6.4 P
Page 2042 and 2043:
ARMv4 and ARMv5 Differences Memory
Page 2044 and 2045:
ARMv4 and ARMv5 Differences H.7.1 O
Page 2046 and 2047:
ARMv4 and ARMv5 Differences H.7.3 c
Page 2048 and 2049:
ARMv4 and ARMv5 Differences For det
Page 2050 and 2051:
ARMv4 and ARMv5 Differences Excludi
Page 2052 and 2053:
ARMv4 and ARMv5 Differences Z, bit
Page 2054 and 2055:
ARMv4 and ARMv5 Differences In ARMv
Page 2056 and 2057:
ARMv4 and ARMv5 Differences c2, Mem
Page 2058 and 2059:
ARMv4 and ARMv5 Differences MRC p15
Page 2060 and 2061:
ARMv4 and ARMv5 Differences Encodin
Page 2062 and 2063:
ARMv4 and ARMv5 Differences Test an
Page 2064 and 2065:
ARMv4 and ARMv5 Differences H.7.11
Page 2066 and 2067:
ARMv4 and ARMv5 Differences Reading
Page 2068 and 2069:
ARMv4 and ARMv5 Differences The 32
Page 2070 and 2071:
ARMv4 and ARMv5 Differences Whether
Page 2072 and 2073:
ARMv4 and ARMv5 Differences The TLB
Page 2074 and 2075:
ARMv4 and ARMv5 Differences where a
Page 2076 and 2077:
ARMv4 and ARMv5 Differences AppxH-6
Page 2078 and 2079:
Pseudocode Definition I.1 Instructi
Page 2080 and 2081:
Pseudocode Definition I.2 Limitatio
Page 2082 and 2083:
Pseudocode Definition A special for
Page 2084 and 2085:
Pseudocode Definition After this de
Page 2086 and 2087:
Pseudocode Definition — a data ty
Page 2088 and 2089:
Pseudocode Definition I.5.3 Bitstri
Page 2090 and 2091:
Pseudocode Definition If x is a bit
Page 2092 and 2093:
Pseudocode Definition Square Root I
Page 2094 and 2095:
Pseudocode Definition UNPREDICTABLE
Page 2096 and 2097:
Pseudocode Definition repeat ... un
Page 2098 and 2099:
Pseudocode Definition I.7 Miscellan
Page 2100 and 2101:
Pseudocode Definition I.7.14 Coproc
Page 2102 and 2103:
Pseudocode Definition I.7.28 Memory
Page 2104 and 2105:
Pseudocode Index J.1 Pseudocode ope
Page 2106 and 2107:
Pseudocode Index Operator Meaning S
Page 2108 and 2109:
Pseudocode Index J.2 Pseudocode fun
Page 2110 and 2111:
Pseudocode Index CheckTLB() Check w
Page 2112 and 2113:
Pseudocode Index DecodeImmShift() D
Page 2114 and 2115:
Pseudocode Index FPRecipEstimate()
Page 2116 and 2117:
Pseudocode Index IsOnes() Test for
Page 2118 and 2119:
Pseudocode Index R[] Access the mai
Page 2120 and 2121:
Pseudocode Index TakeSMCException()
Page 2122 and 2123:
Pseudocode Index WRPMatch() Check w
Page 2124 and 2125:
Register Index K.1 Register index T
Page 2126 and 2127:
Register Index Register In a Descri
Page 2128 and 2129:
Page 2130 and 2131:
Page 2132 and 2133:
Page 2134 and 2135:
Page 2136 and 2137:
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Page 2142 and 2143:
Page 2144 and 2145:
Page 2146 and 2147:
Glossary Atomicity Is a term that d
Page 2148 and 2149:
Glossary Conditional execution Mean
Page 2150 and 2151:
Glossary High vectors Are alternati
Page 2152 and 2153:
Glossary Physical address (PA) Iden
Page 2154 and 2155:
Glossary Round towards Zero (RZ) mo
Page 2156 and 2157:
Glossary Temporal locality Is the o
Page 2158:
Glossary Word Is a 32-bit data item
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