ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
Instruction Details
LDC{2}{L} , , Normal form with P = 1, W = 0
LDC{2}{L} , , [PC,#+/-] Alternative form with P = 1, W = 0
LDC{2}{L} , , [PC], Unindexed form with P = 0, U = 1, W = 0
where:
2 If specified, selects encoding T2 / A2. If omitted, selects encoding T1 / A1.
L If specified, selects the D == 1 form of the encoding. If omitted, selects the D == 0 form.
See Standard assembler syntax fields on page A8-7. An ARM LDC2 instruction must be
unconditional.
The name of the coprocessor. The standard generic coprocessor names are p0, p1, …, p15.
The coprocessor destination register.
The label of the literal data item that is to be loaded into . The assembler calculates the
required value of the offset from the Align(PC,4) value of this instruction to the label.
Permitted values of the offset are multiples of 4 in the range -1020 to 1020.
If the offset is zero or positive, imm32 is equal to the offset and add == TRUE.
If the offset is negative, imm32 is equal to minus the offset and add == FALSE.
The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be
specified separately, including permitting a subtraction of 0 that cannot be specified using the normal
syntax. For more information, see Use of labels in UAL instruction syntax on page A4-5.
The unindexed form is permitted for the ARM instruction set only. In it, is a coprocessor option,
written as an integer 0-255 enclosed in { } and encoded in imm8.
The pre-UAL syntax LDCL is equivalent to LDCL.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
if !Coproc_Accepted(cp, ThisInstr()) then
GenerateCoprocessorException();
else
NullCheckIfThumbEE(15);
offset_addr = if add then (Align(PC,4) + imm32) else (Align(PC,4) - imm32);
address = if index then offset_addr else Align(PC,4);
repeat
Coproc_SendLoadedWord(MemA[address,4], cp, ThisInstr()); address = address + 4;
until Coproc_DoneLoading(cp, ThisInstr());
Exceptions
Undefined Instruction, Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-109