ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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The System Level Programmers’ Model Jazelle state exit The processor exits Jazelle state in IMPLEMENTATION DEFINED circumstances. Typically, this is due to attempted execution of a bytecode instruction that the implementation cannot handle in hardware, or that generates one of the Java exceptions described in Lindholm and Yellin, The Java Virtual Machine Specification 2nd Edition. On exit from Jazelle state, various processor registers contain SUBARCHITECTURE DEFINED values, enabling the EJVM to resume software execution of the bytecode program correctly. The processor also exits Jazelle state when a processor exception occurs. The CPSR is copied to the banked SPSR for the exception mode, so the banked SPSR contains J == 1 and T == 0, and Jazelle state is restored on return from the exception when the SPSR is copied back into the CPSR. With the restriction that Jazelle state execution can modify only Application Level registers, this ensures that all registers are correctly preserved and can be restored by the exception handlers. Configuration and control registers can be modified in the exception handler itself as described in Jazelle state configuration and control on page B1-77 and Jazelle OS Control Register (JOSCR) on page B1-77. Specific considerations apply to processor exceptions, see Exception handling in the Jazelle extension on page B1-74. It is IMPLEMENTATION DEFINED whether Jazelle extension hardware contains state that is both: modified during Jazelle state execution held outside the Application Level registers during Jazelle state execution. If such state exists, the implementation must: Initialize the state from one or more of the Application Level registers whenever Jazelle state is entered, whether as the result of: — the execution of a BXJ instruction — returning from a processor exception. Write the state into one or more of the Application Level registers whenever Jazelle state is exited, whether as a result of taking a processor exception or of IMPLEMENTATION DEFINED circumstances. Ensure that the mechanism for writing the state into Application Level registers on taking a processor exception, and initializing the state from Application Level registers on returning from that exception, ensures that the state is correctly preserved and restored over the exception. Additional Jazelle state restrictions The Jazelle extension hardware must obey the following restrictions: It must not change processor mode other than by taking one of the standard ARM processor exceptions. It must not access banked versions of registers other than the ones belonging to the processor mode in which it is entered. It must not do anything that is illegal for an UNPREDICTABLE instruction. That is, it must not: — generate a security loophole — halt or hang the processor or any other part of the system. B1-82 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
The System Level Programmers’ Model As a result of these requirements, Jazelle state can be entered from User mode without risking a breach of OS security. In addition, Jazelle state execution is UNPREDICTABLE in FIQ mode. ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-83
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® ARM Architecture Reference Manua
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This ARM Architecture Reference Man
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Contents ARM Architecture Reference
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Contents Chapter A6 Thumb Instructi
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Contents C1.3 Security Extensions a
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Contents Appendix D Deprecated and
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Preface This preface summarizes the
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Using this manual The information i
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Part D, Appendices This manual cont
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Assembler syntax descriptions This
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Feedback ARM welcomes feedback on i
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Part A Application Level Architectu
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Introduction to the ARM Architectur
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Application Level Programmers’ Mo
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Application Level Memory Model A3.1
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Application Level Memory Model The
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Application Level Memory Model Reve
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Application Level Memory Model When
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Application Level Memory Model Open
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Application Level Memory Model Excl
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Application Level Memory Model If t
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Application Level Memory Model Memo
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Application Level Memory Model If a
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Application Level Memory Model Non-
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Application Level Memory Model Writ
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Application Level Memory Model All
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Application Level Memory Model To e
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Application Level Memory Model a re
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Application Level Memory Model A1 I
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Application Level Memory Model The
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Application Level Memory Model In a
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The Instruction Sets A4.1 About the
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The Instruction Sets A4.2 Unified A
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The Instruction Sets This alternati
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The Instruction Sets A4.4 Data-proc
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The Instruction Sets Instruction Mn
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The Instruction Sets Signed Most Si
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The Instruction Sets A4.4.5 Packing
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The Instruction Sets A4.4.7 Paralle
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The Instruction Sets A4.5 Status re
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The Instruction Sets A4.6.3 Unprivi
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The Instruction Sets A4.7 Load/stor
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The Instruction Sets A4.9 Exception
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The Instruction Sets A4.11 Advanced
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The Instruction Sets Table A4-14 El
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The Instruction Sets A4.13 Advanced
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The Instruction Sets Table A4-16 Ad
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The Instruction Sets A4.13.4 Advanc
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The Instruction Sets A4.13.6 Miscel
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The Instruction Sets A4.14 VFP data
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ARM Instruction Set Encoding A5.1 A
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ARM Instruction Set Encoding A5.2 D
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ARM Instruction Set Encoding Table
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ARM Instruction Set Encoding A5.2.3
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ARM Instruction Set Encoding Carry
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ARM Instruction Set Encoding 1 xx1x
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ARM Instruction Set Encoding A5.6 S
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ARM Instruction Set Encoding A5.7 U
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ARM Instruction Set Encoding 110x00
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Thumb Instruction Set Encoding A6.1
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Thumb Instruction Set Encoding If t
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Thumb Instruction Set Encoding If-T
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Thumb Instruction Set Encoding Tabl
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Thumb Instruction Set Encoding Carr
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Thumb Instruction Set Encoding 0100
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Thumb Instruction Set Encoding Tabl
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Thumb Instruction Set Encoding op1
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Thumb Instruction Set Encoding A6-4
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Advanced SIMD and VFP Instruction E
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Instruction Details A8.1 Format of
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Instruction Details A8.1.4 Assemble
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Instruction Details A8.1.6 Exceptio
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Instruction Details A8.3 Conditiona
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Instruction Details A8.4 Shifts app
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Instruction Details if imm5 == ‘0
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Instruction Details A8.6 Alphabetic
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Instruction Details A8.6.2 ADC (reg
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Instruction Details A8.6.3 ADC (reg
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Instruction Details A8.6.4 ADD (imm
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Instruction Details A8.6.5 ADD (imm
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Instruction Details A8.6.6 ADD (reg
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Instruction Details A8.6.7 ADD (reg
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Instruction Details A8.6.8 ADD (SP
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Instruction Details A8.6.9 ADD (SP
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Instruction Details A8.6.10 ADR Thi
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Instruction Details A8.6.11 AND (im
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Instruction Details A8.6.12 AND (re
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Instruction Details A8.6.13 AND (re
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Instruction Details A8.6.14 ASR (im
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Instruction Details A8.6.15 ASR (re
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Instruction Details A8.6.16 B Branc
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Instruction Details A8.6.17 BFC Bit
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Instruction Details A8.6.18 BFI Bit
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Instruction Details A8.6.19 BIC (im
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Instruction Details A8.6.20 BIC (re
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Instruction Details A8.6.21 BIC (re
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Instruction Details A8.6.22 BKPT Br
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Instruction Details A8.6.23 BL, BLX
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Instruction Details A8.6.24 BLX (re
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Instruction Details A8.6.25 BX Bran
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Instruction Details A8.6.26 BXJ Bra
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Instruction Details A8.6.27 CBNZ, C
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Instruction Details A8.6.28 CDP, CD
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Instruction Details A8.6.29 CHKA A8
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Instruction Details A8.6.31 CLZ Cou
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Instruction Details A8.6.32 CMN (im
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Instruction Details A8.6.33 CMN (re
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Instruction Details A8.6.34 CMN (re
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Instruction Details A8.6.35 CMP (im
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Instruction Details A8.6.36 CMP (re
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Instruction Details A8.6.37 CMP (re
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Instruction Details A8.6.38 CPS A8.
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Instruction Details A8.6.40 DBG Deb
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Instruction Details A8.6.41 DMB Dat
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Instruction Details A8.6.42 DSB Dat
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Instruction Details A8.6.43 ENTERX
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Instruction Details A8.6.45 EOR (re
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Instruction Details A8.6.46 EOR (re
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Instruction Details A8.6.47 F* (for
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Instruction Details A8.6.48 HB, HBL
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Instruction Details A8.6.50 IT If T
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Instruction Details A8.6.51 LDC, LD
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Instruction Details A8.6.52 LDC, LD
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Instruction Details A8.6.53 LDM / L
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Instruction Details A8.6.54 LDMDA /
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Instruction Details A8.6.55 LDMDB /
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Instruction Details A8.6.56 LDMIB /
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Instruction Details A8.6.57 LDR (im
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Instruction Details A8.6.58 LDR (im
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Instruction Details A8.6.59 LDR (li
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Instruction Details A8.6.60 LDR (re
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Instruction Details A8.6.61 LDRB (i
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Instruction Details A8.6.62 LDRB (i
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Instruction Details A8.6.63 LDRB (l
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Instruction Details A8.6.64 LDRB (r
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Instruction Details A8.6.65 LDRBT L
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Instruction Details A8.6.66 LDRD (i
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Instruction Details A8.6.67 LDRD (l
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Instruction Details A8.6.68 LDRD (r
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Instruction Details A8.6.69 LDREX L
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Instruction Details A8.6.70 LDREXB
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Instruction Details A8.6.71 LDREXD
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Instruction Details A8.6.72 LDREXH
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Instruction Details A8.6.73 LDRH (i
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Instruction Details A8.6.74 LDRH (i
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Instruction Details A8.6.75 LDRH (l
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Instruction Details A8.6.76 LDRH (r
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Instruction Details A8.6.77 LDRHT L
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Instruction Details A8.6.78 LDRSB (
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Instruction Details A8.6.81 LDRSBT
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Instruction Details A8.6.82 LDRSH (
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Instruction Details A8.6.85 LDRSHT
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Instruction Details A8.6.86 LDRT Lo
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Instruction Details A8.6.87 LEAVEX
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Instruction Details A8.6.89 LSL (re
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Instruction Details A8.6.90 LSR (im
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Instruction Details A8.6.91 LSR (re
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Instruction Details A8.6.92 MCR, MC
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Instruction Details A8.6.93 MCRR, M
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Instruction Details A8.6.94 MLA Mul
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Instruction Details A8.6.95 MLS Mul
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Instruction Details A8.6.96 MOV (im
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Instruction Details A8.6.97 MOV (re
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Instruction Details A8.6.98 MOV (sh
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Instruction Details A8.6.99 MOVT Mo
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Instruction Details A8.6.100 MRC, M
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Instruction Details A8.6.101 MRRC,
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Instruction Details A8.6.102 MRS Mo
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Instruction Details A8.6.103 MSR (i
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Instruction Details A8.6.104 MSR (r
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Instruction Details A8.6.105 MUL Mu
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Instruction Details A8.6.106 MVN (i
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Instruction Details A8.6.107 MVN (r
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Instruction Details A8.6.108 MVN (r
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Instruction Details A8.6.109 NEG Ne
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Instruction Details A8.6.110 NOP No
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Instruction Details A8.6.111 ORN (i
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Instruction Details A8.6.112 ORN (r
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Instruction Details A8.6.113 ORR (i
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Instruction Details A8.6.114 ORR (r
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Instruction Details A8.6.115 ORR (r
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Instruction Details A8.6.116 PKH Pa
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Instruction Details A8.6.117 PLD, P
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Instruction Details A8.6.118 PLD (l
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Instruction Details A8.6.119 PLD, P
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Instruction Details A8.6.120 PLI (i
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Instruction Details A8.6.121 PLI (r
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Instruction Details A8.6.122 POP Po
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Instruction Details A8.6.123 PUSH P
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Instruction Details A8.6.124 QADD S
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Instruction Details A8.6.125 QADD16
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Instruction Details A8.6.126 QADD8
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Instruction Details A8.6.127 QASX S
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Instruction Details A8.6.128 QDADD
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Instruction Details A8.6.129 QDSUB
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Instruction Details A8.6.130 QSAX S
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Instruction Details A8.6.131 QSUB S
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Instruction Details A8.6.132 QSUB16
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Instruction Details A8.6.133 QSUB8
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Instruction Details A8.6.134 RBIT R
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Instruction Details A8.6.135 REV By
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Instruction Details A8.6.136 REV16
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Instruction Details A8.6.137 REVSH
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Instruction Details A8.6.138 RFE Re
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Instruction Details A8.6.140 ROR (r
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Instruction Details A8.6.141 RRX Ro
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Instruction Details A8.6.142 RSB (i
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Instruction Details A8.6.143 RSB (r
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Instruction Details A8.6.144 RSB (r
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Instruction Details A8.6.145 RSC (i
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Instruction Details A8.6.146 RSC (r
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Instruction Details A8.6.147 RSC (r
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Instruction Details A8.6.148 SADD16
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Instruction Details A8.6.149 SADD8
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Instruction Details A8.6.150 SASX S
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Instruction Details A8.6.151 SBC (i
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Instruction Details A8.6.152 SBC (r
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Instruction Details A8.6.153 SBC (r
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Instruction Details A8.6.154 SBFX S
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Instruction Details A8.6.155 SDIV S
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Instruction Details A8.6.156 SEL Se
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Instruction Details A8.6.157 SETEND
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Instruction Details A8.6.158 SEV Se
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Instruction Details A8.6.159 SHADD1
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Instruction Details A8.6.160 SHADD8
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Instruction Details A8.6.161 SHASX
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Instruction Details A8.6.162 SHSAX
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Instruction Details A8.6.163 SHSUB1
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Instruction Details A8.6.164 SHSUB8
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Instruction Details A8.6.165 SMC (p
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Instruction Details A8.6.167 SMLAD
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Instruction Details A8.6.168 SMLAL
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Instruction Details A8.6.169 SMLALB
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Instruction Details A8.6.170 SMLALD
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Instruction Details A8.6.171 SMLAWB
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Instruction Details A8.6.172 SMLSD
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Instruction Details A8.6.173 SMLSLD
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Instruction Details A8.6.175 SMMLS
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Instruction Details A8.6.176 SMMUL
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Instruction Details A8.6.177 SMUAD
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Instruction Details A8.6.178 SMULBB
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Instruction Details A8.6.179 SMULL
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Instruction Details A8.6.180 SMULWB
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Instruction Details A8.6.182 SRS A8
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Instruction Details A8.6.184 SSAT16
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Instruction Details A8.6.185 SSAX S
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Instruction Details A8.6.186 SSUB16
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Instruction Details A8.6.187 SSUB8
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Instruction Details A8.6.188 STC, S
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Instruction Details A8.6.189 STM /
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Instruction Details A8.6.190 STMDA
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Instruction Details A8.6.191 STMDB
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Instruction Details A8.6.192 STMIB
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Instruction Details A8.6.194 STR (i
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Instruction Details A8.6.196 STRB (
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Instruction Details A8.6.199 STRBT
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Instruction Details A8.6.200 STRD (
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Instruction Details A8.6.201 STRD (
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Instruction Details A8.6.202 STREX
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Instruction Details A8.6.203 STREXB
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Instruction Details A8.6.204 STREXD
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Instruction Details A8.6.205 STREXH
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Instruction Details A8.6.206 STRH (
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Instruction Details A8.6.209 STRHT
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Instruction Details A8.6.210 STRT S
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Instruction Details A8.6.211 SUB (i
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Instruction Details A8.6.212 SUB (i
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Instruction Details A8.6.213 SUB (r
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Instruction Details A8.6.214 SUB (r
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Instruction Details A8.6.215 SUB (S
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Instruction Details A8.6.216 SUB (S
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Instruction Details A8.6.217 SUBS P
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Instruction Details A8.6.219 SWP, S
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Instruction Details A8.6.220 SXTAB
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Instruction Details A8.6.221 SXTAB1
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Instruction Details A8.6.222 SXTAH
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Instruction Details A8.6.223 SXTB S
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Instruction Details A8.6.224 SXTB16
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Instruction Details A8.6.225 SXTH S
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Instruction Details A8.6.226 TBB, T
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Instruction Details A8.6.227 TEQ (i
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Instruction Details A8.6.228 TEQ (r
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Instruction Details A8.6.229 TEQ (r
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Instruction Details A8.6.230 TST (i
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Instruction Details A8.6.231 TST (r
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Instruction Details A8.6.232 TST (r
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Instruction Details A8.6.233 UADD16
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Instruction Details A8.6.234 UADD8
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Instruction Details A8.6.235 UASX U
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Instruction Details A8.6.236 UBFX U
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Instruction Details A8.6.237 UDIV U
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Instruction Details A8.6.238 UHADD1
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Instruction Details A8.6.239 UHADD8
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Instruction Details A8.6.240 UHASX
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Instruction Details A8.6.241 UHSAX
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Instruction Details A8.6.242 UHSUB1
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Instruction Details A8.6.243 UHSUB8
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Instruction Details A8.6.244 UMAAL
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Instruction Details A8.6.245 UMLAL
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Instruction Details A8.6.246 UMULL
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Instruction Details A8.6.247 UQADD1
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Instruction Details A8.6.248 UQADD8
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Instruction Details A8.6.249 UQASX
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Instruction Details A8.6.250 UQSAX
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Instruction Details A8.6.251 UQSUB1
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Instruction Details A8.6.252 UQSUB8
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Instruction Details A8.6.253 USAD8
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Instruction Details A8.6.254 USADA8
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Instruction Details A8.6.255 USAT U
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Instruction Details A8.6.256 USAT16
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Instruction Details A8.6.257 USAX U
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Instruction Details A8.6.258 USUB16
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Instruction Details A8.6.259 USUB8
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Instruction Details A8.6.260 UXTAB
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Instruction Details A8.6.261 UXTAB1
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Instruction Details A8.6.262 UXTAH
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Instruction Details A8.6.263 UXTB U
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Instruction Details A8.6.264 UXTB16
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Instruction Details A8.6.265 UXTH U
Page 838 and 839:
Instruction Details A8.6.266 VABA,
Page 840 and 841:
Instruction Details A8.6.267 VABD,
Page 842 and 843:
Instruction Details A8.6.268 VABD (
Page 844 and 845:
Instruction Details A8.6.269 VABS V
Page 846 and 847:
Instruction Details A8.6.270 VACGE,
Page 848 and 849:
Instruction Details A8.6.271 VADD (
Page 850 and 851:
Instruction Details A8.6.272 VADD (
Page 852 and 853:
Instruction Details A8.6.273 VADDHN
Page 854 and 855:
Instruction Details A8.6.274 VADDL,
Page 856 and 857:
Instruction Details A8.6.275 VAND (
Page 858 and 859:
Instruction Details A8.6.277 VBIC (
Page 860 and 861:
Instruction Details A8.6.278 VBIC (
Page 862 and 863:
Instruction Details A8.6.279 VBIF,
Page 864 and 865:
Instruction Details A8.6.280 VCEQ (
Page 866 and 867:
Instruction Details A8.6.281 VCEQ (
Page 868 and 869:
Instruction Details A8.6.282 VCGE (
Page 870 and 871:
Instruction Details A8.6.283 VCGE (
Page 872 and 873:
Instruction Details A8.6.284 VCGT (
Page 874 and 875:
Instruction Details A8.6.285 VCGT (
Page 876 and 877:
Instruction Details A8.6.286 VCLE (
Page 878 and 879:
Instruction Details A8.6.288 VCLS V
Page 880 and 881:
Instruction Details A8.6.289 VCLT (
Page 882 and 883:
Instruction Details A8.6.291 VCLZ V
Page 884 and 885:
Instruction Details A8.6.292 VCMP,
Page 886 and 887:
Instruction Details A8.6.293 VCNT T
Page 888 and 889:
Instruction Details A8.6.294 VCVT (
Page 890 and 891:
Instruction Details A8.6.295 VCVT,
Page 892 and 893:
Page 894 and 895:
Page 896 and 897:
Page 898 and 899:
Page 900 and 901:
Instruction Details A8.6.300 VCVTB,
Page 902 and 903:
Instruction Details A8.6.301 VDIV T
Page 904 and 905:
Instruction Details A8.6.302 VDUP (
Page 906 and 907:
Instruction Details A8.6.303 VDUP (
Page 908 and 909:
Instruction Details A8.6.304 VEOR V
Page 910 and 911:
Instruction Details A8.6.305 VEXT V
Page 912 and 913:
Instruction Details A8.6.306 VHADD,
Page 914 and 915:
Instruction Details A8.6.307 VLD1 (
Page 916 and 917:
Page 918 and 919:
Page 920 and 921:
Page 922 and 923:
Page 924 and 925:
Page 926 and 927:
Page 928 and 929:
Page 930 and 931:
Page 932 and 933:
Page 934 and 935:
Page 936 and 937:
Page 938 and 939:
Instruction Details A8.6.319 VLDM V
Page 940 and 941:
Instruction Details A8.6.320 VLDR T
Page 942 and 943:
Instruction Details A8.6.321 VMAX,
Page 944 and 945:
Instruction Details A8.6.322 VMAX,
Page 946 and 947:
Instruction Details A8.6.323 VMLA,
Page 948 and 949:
Page 950 and 951:
Page 952 and 953:
Instruction Details A8.6.326 VMOV (
Page 954 and 955:
Page 956 and 957:
Page 958 and 959:
Page 960 and 961:
Page 962 and 963:
Page 964 and 965:
Page 966 and 967:
Instruction Details A8.6.333 VMOVL
Page 968 and 969:
Instruction Details A8.6.334 VMOVN
Page 970 and 971:
Instruction Details A8.6.335 VMRS M
Page 972 and 973:
Instruction Details A8.6.336 VMSR M
Page 974 and 975:
Instruction Details A8.6.337 VMUL,
Page 976 and 977:
Instruction Details A8.6.338 VMUL (
Page 978 and 979:
Instruction Details A8.6.339 VMUL,
Page 980 and 981:
Instruction Details A8.6.340 VMVN (
Page 982 and 983:
Instruction Details A8.6.341 VMVN (
Page 984 and 985:
Instruction Details A8.6.342 VNEG V
Page 986 and 987:
Instruction Details A8.6.343 VNMLA,
Page 988 and 989:
Instruction Details A8.6.344 VORN (
Page 990 and 991:
Instruction Details A8.6.346 VORR (
Page 992 and 993:
Instruction Details A8.6.347 VORR (
Page 994 and 995:
Instruction Details A8.6.348 VPADAL
Page 996 and 997:
Instruction Details A8.6.349 VPADD
Page 998 and 999:
Instruction Details A8.6.350 VPADD
Page 1000 and 1001:
Instruction Details A8.6.351 VPADDL
Page 1002 and 1003:
Instruction Details A8.6.352 VPMAX,
Page 1004 and 1005:
Instruction Details A8.6.353 VPMAX,
Page 1006 and 1007:
Instruction Details A8.6.354 VPOP V
Page 1008 and 1009:
Instruction Details A8.6.355 VPUSH
Page 1010 and 1011:
Instruction Details A8.6.356 VQABS
Page 1012 and 1013:
Instruction Details A8.6.357 VQADD
Page 1014 and 1015:
Instruction Details A8.6.358 VQDMLA
Page 1016 and 1017:
Instruction Details A8.6.359 VQDMUL
Page 1018 and 1019:
Instruction Details A8.6.360 VQDMUL
Page 1020 and 1021:
Instruction Details A8.6.361 VQMOVN
Page 1022 and 1023:
Instruction Details A8.6.362 VQNEG
Page 1024 and 1025:
Instruction Details A8.6.363 VQRDMU
Page 1026 and 1027:
Instruction Details A8.6.364 VQRSHL
Page 1028 and 1029:
Instruction Details A8.6.365 VQRSHR
Page 1030 and 1031:
Instruction Details A8.6.366 VQSHL
Page 1032 and 1033:
Instruction Details A8.6.367 VQSHL,
Page 1034 and 1035:
Instruction Details A8.6.368 VQSHRN
Page 1036 and 1037:
Instruction Details A8.6.369 VQSUB
Page 1038 and 1039:
Instruction Details A8.6.370 VRADDH
Page 1040 and 1041:
Instruction Details A8.6.371 VRECPE
Page 1042 and 1043:
Instruction Details A8.6.372 VRECPS
Page 1044 and 1045:
Instruction Details A8.6.373 VREV16
Page 1046 and 1047:
Instruction Details A8.6.374 VRHADD
Page 1048 and 1049:
Instruction Details A8.6.375 VRSHL
Page 1050 and 1051:
Instruction Details A8.6.376 VRSHR
Page 1052 and 1053:
Instruction Details A8.6.377 VRSHRN
Page 1054 and 1055:
Instruction Details A8.6.378 VRSQRT
Page 1056 and 1057:
Instruction Details A8.6.379 VRSQRT
Page 1058 and 1059:
Instruction Details A8.6.380 VRSRA
Page 1060 and 1061:
Instruction Details A8.6.381 VRSUBH
Page 1062 and 1063:
Instruction Details A8.6.382 VSHL (
Page 1064 and 1065:
Instruction Details A8.6.383 VSHL (
Page 1066 and 1067:
Instruction Details A8.6.384 VSHLL
Page 1068 and 1069:
Instruction Details A8.6.385 VSHR V
Page 1070 and 1071:
Instruction Details A8.6.386 VSHRN
Page 1072 and 1073:
Instruction Details A8.6.387 VSLI V
Page 1074 and 1075:
Instruction Details A8.6.388 VSQRT
Page 1076 and 1077:
Instruction Details A8.6.389 VSRA V
Page 1078 and 1079:
Instruction Details A8.6.390 VSRI V
Page 1080 and 1081:
Instruction Details A8.6.391 VST1 (
Page 1082 and 1083:
Page 1084 and 1085:
Page 1086 and 1087:
Page 1088 and 1089:
Page 1090 and 1091:
Page 1092 and 1093:
Page 1094 and 1095:
Page 1096 and 1097:
Instruction Details A8.6.399 VSTM V
Page 1098 and 1099:
Instruction Details A8.6.400 VSTR T
Page 1100 and 1101:
Instruction Details A8.6.401 VSUB (
Page 1102 and 1103:
Instruction Details A8.6.402 VSUB (
Page 1104 and 1105:
Instruction Details A8.6.403 VSUBHN
Page 1106 and 1107:
Instruction Details A8.6.404 VSUBL,
Page 1108 and 1109:
Instruction Details A8.6.405 VSWP V
Page 1110 and 1111:
Instruction Details A8.6.406 VTBL,
Page 1112 and 1113:
Instruction Details A8.6.407 VTRN D
Page 1114 and 1115:
Instruction Details A8.6.408 VTST V
Page 1116 and 1117:
Instruction Details A8.6.409 VUZP V
Page 1118 and 1119:
Instruction Details A8.6.410 VZIP V
Page 1120 and 1121:
Instruction Details A8.6.411 WFE Wa
Page 1122 and 1123:
Instruction Details A8.6.412 WFI Wa
Page 1124 and 1125:
Instruction Details A8.6.413 YIELD
Page 1126 and 1127:
Instruction Details A8-814 Copyrigh
Page 1128 and 1129:
ThumbEE A9.1 The ThumbEE instructio
Page 1130 and 1131:
ThumbEE A9.1.3 Instructions with mo
Page 1132 and 1133:
ThumbEE A9.2 ThumbEE instruction se
Page 1134 and 1135:
ThumbEE A9.4 ThumbEE instructions w
Page 1136 and 1137:
ThumbEE A9.4.2 LDRH (register) Load
Page 1138 and 1139:
ThumbEE A9.4.4 STR (register) Store
Page 1140 and 1141:
ThumbEE A9.5 Additional ThumbEE ins
Page 1142 and 1143:
ThumbEE A9.5.2 HB, HBL Handler Bran
Page 1144 and 1145:
ThumbEE A9.5.4 HBP HBP (Handler Bra
Page 1146 and 1147:
ThumbEE Assembler syntax LDR , [{,
Page 1148 and 1149:
ThumbEE A9-22 Copyright © 1996-199
Page 1151 and 1152:
Chapter B1 The System Level Program
Page 1153 and 1154:
B1.2 System level concepts and term
Page 1155 and 1156:
An exception is described as synchr
Page 1157 and 1158:
Notes on the ARM processor modes Th
Page 1159 and 1160:
B1.3.2 ARM core registers The Syste
Page 1161 and 1162:
Writing to the PC In ARMv7, instruc
Page 1163 and 1164:
LookUpRName() // ============= The
Page 1165 and 1166:
interrupt and asynchronous abort di
Page 1167 and 1168:
Mask bits, bits [8:6] The System Le
Page 1169 and 1170:
The System Level Programmers’ Mod
Page 1171 and 1172:
SPSR[] = bits(32) value if BadMode(
Page 1173 and 1174:
B1.4 Instruction set states The Sys
Page 1175 and 1176:
B1.5 The Security Extensions The Sy
Page 1177 and 1178:
Note It is important to distinguish
Page 1179 and 1180:
The System Level Programmers’ Mod
Page 1181 and 1182: Exception offset Exception that is
Page 1183 and 1184: Operation The System Level Programm
Page 1185 and 1186: Exception Base LR value a Instructi
Page 1187 and 1188: Exception The System Level Programm
Page 1189 and 1190: The System Level Programmers’ Mod
Page 1191 and 1192: B1.6.5 Exception-handling instructi
Page 1193 and 1194: SCR bits FW FIQ Effect on FIQ handl
Page 1203 and 1204: B1.6.13 Secure Monitor Call (SMC) e
Page 1205 and 1206: new_spsr_value = CPSR; The System L
Page 1207 and 1208: CPSR.J = ‘0’; CPSR.T = SCTLR.TE
Page 1217 and 1218: Note The System Level Programmers
Page 1221 and 1222: In addition: The System Level Progr
Page 1223 and 1224: B1.9 Execution environment support
Page 1227 and 1228: Jazelle state configuration and con
Page 1229 and 1230: Controlling entry to Jazelle state
Page 1231: Trivial implementation of the Jazel
Page 1235 and 1236: Chapter B2 Common Memory System Arc
Page 1237 and 1238: B2.2 Caches Common Memory System Ar
Page 1239 and 1240: B2.2.2 Cache behavior Common Memory
Page 1241 and 1242: Common Memory System Architecture F
Page 1243 and 1244: Note Common Memory System Architect
Page 1253 and 1254: implement one of the other permitte
Page 1261 and 1262: B2.3 IMPLEMENTATION DEFINED memory
Page 1265 and 1266: when MemArch_PMSA AlignmentFaultP(a
Page 1269 and 1270: B2.4.7 Exclusive monitors operation
Page 1271 and 1272: B2.4.8 Access permission checking C
Page 1273 and 1274: B2.4.10 Data Abort exception Common
Page 1275 and 1276: Chapter B3 Virtual Memory System Ar
Page 1277 and 1278: Virtual Memory System Architecture
Page 1279 and 1280: B3.2.3 Enabling and disabling the M
Page 1281 and 1282: B3.3 Translation tables Virtual Mem
Page 1283 and 1284:
The other fields in the descriptors
Page 1285 and 1286:
Additional requirements for transla
Page 1287 and 1288:
B3.3.3 Translation table walks Virt
Page 1289 and 1290:
Virtual Memory System Architecture
Page 1291 and 1292:
Translation flow for a Section Virt
Page 1293 and 1294:
Translation flow for a Small page V
Page 1295 and 1296:
B3.3.4 Changing translation table a
Page 1297 and 1298:
B3.4 Address mapping restrictions V
Page 1299 and 1300:
Note Virtual Memory System Architec
Page 1301 and 1302:
B3.5.1 The effect of the Security E
Page 1303 and 1304:
AP[2] AP[1:0] Virtual Memory System
Page 1305 and 1306:
B3.6.3 Domains Virtual Memory Syste
Page 1307 and 1308:
Page 1309 and 1310:
Page 1311 and 1312:
Page 1313 and 1314:
B3.7.4 The effect of the Security E
Page 1315 and 1316:
Section domain fault Section permis
Page 1317 and 1318:
Translation fault There are two typ
Page 1319 and 1320:
B3.8.2 External aborts Virtual Memo
Page 1321 and 1322:
Page 1323 and 1324:
Page 1325 and 1326:
DFSR [10,3:0] a Virtual Memory Syst
Page 1327 and 1328:
B3.9.8 Auxiliary Fault Status Regis
Page 1329 and 1330:
B3.10.2 TLB matching Virtual Memory
Page 1331 and 1332:
In the TLB operations: Virtual Memo
Page 1333 and 1334:
Page 1335 and 1336:
Page 1337 and 1338:
Page 1339 and 1340:
Page 1341 and 1342:
Register and description c1, Secure
Page 1343 and 1344:
Page 1345 and 1346:
Page 1347 and 1348:
CP15 register Virtual Memory System
Page 1349 and 1350:
CP15 register Virtual Memory System
Page 1351 and 1352:
Page 1353 and 1354:
B3.12.6 CP15 c0, ID codes registers
Page 1355 and 1356:
B3.12.7 c0, Main ID Register (MIDR)
Page 1357 and 1358:
Accessing the MIDR Virtual Memory S
Page 1359 and 1360:
B3.12.9 c0, TCM Type Register (TCMT
Page 1361 and 1362:
B3.12.11 c0, Multiprocessor Affinit
Page 1363 and 1364:
Page 1365 and 1366:
B3.12.12 c0, Cache Size ID Register
Page 1367 and 1368:
CtypeX, bits [3(x - 1) + 2:3(x - 1)
Page 1369 and 1370:
B3.12.15 c0, Cache Size Selection R
Page 1371 and 1372:
When the Security Extensions are im
Page 1373 and 1374:
Bit [23] RAO/SBOP. Virtual Memory S
Page 1375 and 1376:
Page 1377 and 1378:
Accessing the SCTLR Virtual Memory
Page 1379 and 1380:
Page 1381 and 1382:
nET, bit [6] Not Early Termination.
Page 1383 and 1384:
The format of the SDER is: 31 Bits
Page 1385 and 1386:
NSASEDIS, bit[15] Disable Non-secur
Page 1387 and 1388:
B3.12.23 CP15 c2 and c3, Memory pro
Page 1389 and 1390:
Page 1391 and 1392:
C, bit [0], ARMv7-A base architectu
Page 1393 and 1394:
Accessing the TTBCR Virtual Memory
Page 1395 and 1396:
B3.12.28 CP15 c5, Fault status regi
Page 1397 and 1398:
Page 1399 and 1400:
Accessing the DFAR Virtual Memory S
Page 1401 and 1402:
Page 1403 and 1404:
Set/way Virtual Memory System Archi
Page 1405 and 1406:
Page 1407 and 1408:
Page 1409 and 1410:
Page 1411 and 1412:
CP15 c7, Data and Instruction Barri
Page 1413 and 1414:
The CP15 c8 TLB maintenance functio
Page 1415 and 1416:
Invalidate TLB entries by MVA all A
Page 1417 and 1418:
The IMPLEMENTATION DEFINED TLB cont
Page 1419 and 1420:
Page 1421 and 1422:
10 Region is WriteThrough, Non-Writ
Page 1423 and 1424:
Page 1425 and 1426:
Page 1427 and 1428:
Page 1429 and 1430:
Accessing the Software Thread ID re
Page 1431 and 1432:
B3.13.3 Address translation Virtual
Page 1433 and 1434:
Page 1435 and 1436:
domain = bits(4) UNKNOWN; sectionno
Page 1437 and 1438:
Chapter B4 Protected Memory System
Page 1439 and 1440:
All addresses are physical addresse
Page 1441 and 1442:
Using the default memory map as a b
Page 1443 and 1444:
Address range Behavior of an implem
Page 1445 and 1446:
B4.2 Memory access control Protecte
Page 1447 and 1448:
B4.3 Memory region attributes Prote
Page 1449 and 1450:
B4.4 PMSA memory aborts Protected M
Page 1451 and 1452:
The MPU fault checking sequence Fig
Page 1453 and 1454:
Parity error reporting Protected Me
Page 1455 and 1456:
B4.5.2 Data Abort exceptions Protec
Page 1457 and 1458:
Reserved encodings in the IFSR and
Page 1459 and 1460:
Protected Memory System Architectur
Page 1461 and 1462:
Page 1463 and 1464:
Unallocated CP15 encodings Protecte
Page 1465 and 1466:
B4.6.4 Meaning of fixed bit values
Page 1467 and 1468:
Page 1469 and 1470:
Architecture, bits [19:16] Table B4
Page 1471 and 1472:
DminLine, bits [19:16] Bit [15] RAO
Page 1473 and 1474:
Page 1475 and 1476:
Page 1477 and 1478:
LineSize, bits [2:0] (Log2(Number o
Page 1479 and 1480:
B4.6.13 c0, IMPLEMENTATION DEFINED
Page 1481 and 1482:
B4.6.16 c1, System Control Register
Page 1483 and 1484:
Bit [20] RAZ/SBZP. Protected Memory
Page 1485 and 1486:
Page 1487 and 1488:
Accessing the ACTLR Protected Memor
Page 1489 and 1490:
Page 1491 and 1492:
Page 1493 and 1494:
The formats of the ADFSR and AIFSR
Page 1495 and 1496:
B4.6.24 CP15 c6, Memory region prog
Page 1497 and 1498:
The DRBAR is: a 32-bit read/write r
Page 1499 and 1500:
RSize, bits [5:1] Protected Memory
Page 1501 and 1502:
Page 1503 and 1504:
Page 1505 and 1506:
Page 1507 and 1508:
Set/way Protected Memory System Arc
Page 1509 and 1510:
Instruction Synchronization Barrier
Page 1511 and 1512:
B4.6.31 CP15 c11, Reserved for TCM
Page 1513 and 1514:
B4.6.35 CP15 c13 Software Thread ID
Page 1515 and 1516:
Page 1517 and 1518:
B4.7.3 Default memory map attribute
Page 1519 and 1520:
Chapter B5 The CPUID Identification
Page 1521 and 1522:
B5.1.2 General features of the CPUI
Page 1523 and 1524:
State1, bits [7:4] The CPUID Identi
Page 1525 and 1526:
Memory-mapped trace model, bits [19
Page 1527 and 1528:
B5.2.4 CP15 c0, Memory Model Featur
Page 1529 and 1530:
c0, Memory Model Feature Register 1
Page 1531 and 1532:
The CPUID Identification Scheme 0b0
Page 1533 and 1534:
Unified TLB, bits [19:16] The CPUID
Page 1535 and 1536:
c0, Memory Model Feature Register 3
Page 1537 and 1538:
Accessing the Memory Model Feature
Page 1539 and 1540:
Multiply instructions The CPUID Ide
Page 1541 and 1542:
The CPUID Identification Scheme Tab
Page 1543 and 1544:
Swap_instrs, bits [3:0] The CPUID I
Page 1545 and 1546:
Endian_instrs, bits [3:0] The CPUID
Page 1547 and 1548:
c0, Instruction Set Attribute Regis
Page 1549 and 1550:
Note The CPUID Identification Schem
Page 1551 and 1552:
Unpriv_instrs, bits [3:0] The CPUID
Page 1553 and 1554:
The CPUID Identification Scheme SW,
Page 1555 and 1556:
Square root, bits [23:20] Divide, b
Page 1557 and 1558:
VFP HPFP, bits[27:24] The CPUID Ide
Page 1559 and 1560:
Chapter B6 System Instructions This
Page 1561 and 1562:
B6.1.1 CPS System Instructions Chan
Page 1563 and 1564:
B6.1.2 LDM (exception return) Syste
Page 1565 and 1566:
B6.1.3 LDM (user registers) System
Page 1567 and 1568:
B6.1.4 LDRBT, LDRHT, LDRSBT, LDRSHT
Page 1569 and 1570:
Assembler syntax MRS , where: See
Page 1571 and 1572:
Operation if ConditionPassed() then
Page 1573 and 1574:
Is a sequence of one or more of the
Page 1575 and 1576:
Assembler syntax RFE{} {!} where:
Page 1577 and 1578:
Assembler syntax SMC # where: See
Page 1579 and 1580:
Assembler syntax SRS{} SP{!}, # whe
Page 1581 and 1582:
Operation if ConditionPassed() then
Page 1583 and 1584:
B6.1.13 SUBS PC, LR and related ins
Page 1585 and 1586:
B6.1.14 VMRS System Instructions Mo
Page 1587 and 1588:
B6.1.15 VMSR System Instructions Mo
Page 1589:
Part C Debug Architecture
Page 1592 and 1593:
Introduction to the ARM Debug Archi
Page 1594 and 1595:
Page 1596 and 1597:
Page 1598 and 1599:
Page 1600 and 1601:
Page 1602 and 1603:
Invasive Debug Authentication C2.1
Page 1604 and 1605:
Invasive Debug Authentication If DB
Page 1606 and 1607:
Debug Events C3.1 About debug event
Page 1608 and 1609:
Debug Events BKPT Instruction Break
Page 1610 and 1611:
Debug Events The following sections
Page 1612 and 1613:
Debug Events Note For IVA compariso
Page 1614 and 1615:
Debug Events Note There is no encod
Page 1616 and 1617:
Debug Events Note v6 Debug does not
Page 1618 and 1619:
Debug Events Interaction of IVA mis
Page 1620 and 1621:
Debug Events Watchpoint Value Regis
Page 1622 and 1623:
Debug Events For the ordering of de
Page 1624 and 1625:
Debug Events Note To understand why
Page 1626 and 1627:
Debug Events Note Normally, excepti
Page 1628 and 1629:
Debug Events Note The FCSE is optio
Page 1630 and 1631:
Debug Events If these guidelines ar
Page 1632 and 1633:
Debug Events BreakpointDebugEvent()
Page 1634 and 1635:
Debug Events when InstrSet_ARM byte
Page 1636 and 1637:
Debug Events if DBGBCR[M] != ‘11
Page 1638 and 1639:
Debug Events else if IsSecure() the
Page 1640 and 1641:
Debug Events // WRPMatch() // =====
Page 1642 and 1643:
Debug Events C3.3 Halting debug eve
Page 1644 and 1645:
Debug Events C3.4 Generation of deb
Page 1646 and 1647:
Debug Events As a result, for an in
Page 1648 and 1649:
Debug Events Debug events must be t
Page 1650 and 1651:
Debug Exceptions C4.1 About debug e
Page 1652 and 1653:
Debug Exceptions C4.2 Effects of de
Page 1654 and 1655:
Debug Exceptions C4-6 Copyright ©
Page 1656 and 1657:
Debug State C5.1 About Debug state
Page 1658 and 1659:
Debug State 3. The processor signal
Page 1660 and 1661:
Debug State the Interrupt Status Re
Page 1662 and 1663:
Debug State Note This rule also app
Page 1664 and 1665:
Debug State A coprocessor can impos
Page 1666 and 1667:
Debug State C5.4.2 Data-processing
Page 1668 and 1669:
Debug State C5.5.2 Altering CPSR pr
Page 1670 and 1671:
Debug State This is a particular ca
Page 1672 and 1673:
Debug State Any CP14 or CP15 regist
Page 1674 and 1675:
Debug State C5.7 Exceptions in Debu
Page 1676 and 1677:
Debug State Asynchronous abort The
Page 1678 and 1679:
Debug State C5.8 Memory system beha
Page 1680 and 1681:
Debug State For more information ab
Page 1682 and 1683:
Debug State C5.9 Leaving Debug stat
Page 1684 and 1685:
Debug State C5-30 Copyright © 1996
Page 1686 and 1687:
Debug Register Interfaces C6.1 Abou
Page 1688 and 1689:
Debug Register Interfaces C6.2 Rese
Page 1690 and 1691:
Debug Register Interfaces To have f
Page 1692 and 1693:
Debug Register Interfaces the exter
Page 1694 and 1695:
Debug Register Interfaces The subse
Page 1696 and 1697:
Debug Register Interfaces The perfo
Page 1698 and 1699:
Debug Register Interfaces DSB ISB ;
Page 1700 and 1701:
Debug Register Interfaces C6.2.4 Re
Page 1702 and 1703:
Debug Register Interfaces C6.3 Debu
Page 1704 and 1705:
Debug Register Interfaces Register
Page 1706 and 1707:
Debug Register Interfaces accesses,
Page 1708 and 1709:
Debug Register Interfaces C6.4 Sync
Page 1710 and 1711:
Debug Register Interfaces C6.5 Acce
Page 1712 and 1713:
Debug Register Interfaces Debug Sof
Page 1714 and 1715:
Debug Register Interfaces It the De
Page 1716 and 1717:
Debug Register Interfaces C6.6 The
Page 1718 and 1719:
Debug Register Interfaces With some
Page 1720 and 1721:
Debug Register Interfaces C6.6.3 CP
Page 1722 and 1723:
Debug Register Interfaces v7 Debug
Page 1724 and 1725:
Debug Register Interfaces Sticky Po
Page 1726 and 1727:
Debug Register Interfaces In v6 Deb
Page 1728 and 1729:
Debug Register Interfaces If the me
Page 1730 and 1731:
Debug Register Interfaces Meanings
Page 1732 and 1733:
Debug Register Interfaces Access pe
Page 1734 and 1735:
Debug Register Interfaces Permissio
Page 1736 and 1737:
Debug Register Interfaces C6-52 Cop
Page 1738 and 1739:
Non-invasive Debug Authentication C
Page 1740 and 1741:
Page 1742 and 1743:
Page 1744 and 1745:
Page 1746 and 1747:
Page 1748 and 1749:
Sample-based Profiling C8.1 Program
Page 1750 and 1751:
Sample-based Profiling If an instru
Page 1752 and 1753:
Performance Monitors C9.1 About the
Page 1754 and 1755:
Performance Monitors C9.2 Status in
Page 1756 and 1757:
Performance Monitors C9.4 Behavior
Page 1758 and 1759:
Performance Monitors C9.6 Interacti
Page 1760 and 1761:
Performance Monitors C9.8 CP15 c9 r
Page 1762 and 1763:
Performance Monitors C9.9 Access pe
Page 1764 and 1765:
Performance Monitors from refilling
Page 1766 and 1767:
Performance Monitors 0x10 Branch mi
Page 1768 and 1769:
Performance Monitors C9-18 Copyrigh
Page 1770 and 1771:
Debug Registers Reference C10.1 Acc
Page 1772 and 1773:
Debug Registers Reference BRPs, bit
Page 1774 and 1775:
Debug Registers Reference Variant,
Page 1776 and 1777:
Debug Registers Reference This regi
Page 1778 and 1779:
Debug Registers Reference C10.3 Con
Page 1780 and 1781:
Debug Registers Reference RXfull_l,
Page 1782 and 1783:
Debug Registers Reference Note The
Page 1784 and 1785:
Debug Registers Reference UDCCdis,
Page 1786 and 1787:
Debug Registers Reference Bit [8],
Page 1788 and 1789:
Debug Registers Reference HALTED, b
Page 1790 and 1791:
Debug Registers Reference The ready
Page 1792 and 1793:
Debug Registers Reference Fast mode
Page 1794 and 1795:
Debug Registers Reference MOE bits
Page 1796 and 1797:
Debug Registers Reference C10.3.2 W
Page 1798 and 1799:
Debug Registers Reference Clear Sti
Page 1800 and 1801:
Debug Registers Reference In v6 Deb
Page 1802 and 1803:
Debug Registers Reference DBGnoPWRD
Page 1804 and 1805:
Debug Registers Reference When the
Page 1806 and 1807:
Debug Registers Reference C10.3.6 P
Page 1808 and 1809:
Debug Registers Reference C10.4 Ins
Page 1810 and 1811:
Debug Registers Reference Access mo
Page 1812 and 1813:
Debug Registers Reference Access to
Page 1814 and 1815:
Debug Registers Reference C10.4.3 I
Page 1816 and 1817:
Debug Registers Reference C10.5 Sof
Page 1818 and 1819:
Debug Registers Reference Address r
Page 1820 and 1821:
Debug Registers Reference DBGBCR[8:
Page 1822 and 1823:
Debug Registers Reference Security
Page 1824 and 1825:
Debug Registers Reference Table C10
Page 1826 and 1827:
Debug Registers Reference BRP type
Page 1828 and 1829:
Debug Registers Reference The gener
Page 1830 and 1831:
Debug Registers Reference This fiel
Page 1832 and 1833:
Debug Registers Reference 0b10 Matc
Page 1834 and 1835:
Debug Registers Reference — If DB
Page 1836 and 1837:
Debug Registers Reference 31 8 Rese
Page 1838 and 1839:
Debug Registers Reference Bits [7:6
Page 1840 and 1841:
Debug Registers Reference For more
Page 1842 and 1843:
Page 1844 and 1845:
Debug Registers Reference The forma
Page 1846 and 1847:
Page 1848 and 1849:
Debug Registers Reference C10.7 Mem
Page 1850 and 1851:
Debug Registers Reference Cache lin
Page 1852 and 1853:
Page 1854 and 1855:
Debug Registers Reference TLB loadi
Page 1856 and 1857:
Debug Registers Reference C10.8 Man
Page 1858 and 1859:
Debug Registers Reference Some of t
Page 1860 and 1861:
Debug Registers Reference C10.8.3 C
Page 1862 and 1863:
Debug Registers Reference C10.8.5 L
Page 1864 and 1865:
Debug Registers Reference C10.8.7 A
Page 1866 and 1867:
Debug Registers Reference If a proc
Page 1868 and 1869:
Debug Registers Reference Figure C1
Page 1870 and 1871:
Debug Registers Reference Uses JEP
Page 1872 and 1873:
Debug Registers Reference Preamble
Page 1874 and 1875:
Page 1876 and 1877:
Debug Registers Reference C10.9.2 c
Page 1878 and 1879:
Debug Registers Reference Bits [30:
Page 1880 and 1881:
Page 1882 and 1883:
Page 1884 and 1885:
Page 1886 and 1887:
Debug Registers Reference C10.9.11
Page 1888 and 1889:
Page 1891 and 1892:
Appendix A Recommended External Deb
Page 1893 and 1894:
A.1.1 Authentication signals DBGEN,
Page 1895 and 1896:
A.1.2 Run-control and cross-trigger
Page 1897 and 1898:
DBGRESTART DBGRESTARTED The numbers
Page 1899 and 1900:
A.1.4 COMMRX and COMMTX Recommended
Page 1901 and 1902:
Recommended External Debug Interfac
Page 1903 and 1904:
A.2 Recommended debug slave port Th
Page 1905 and 1906:
A.2.1 PADDRDBG PADDRDBG selects the
Page 1907 and 1908:
Appendix B Common VFP Subarchitectu
Page 1909 and 1910:
B.2 Introduction to the Common VFP
Page 1911 and 1912:
Note Common VFP Subarchitecture Spe
Page 1913 and 1914:
Common VFP Subarchitecture Specific
Page 1915 and 1916:
For scalar CDP instructions: Common
Page 1917 and 1918:
B.4 Support code requirements Commo
Page 1919 and 1920:
Page 1921 and 1922:
Page 1923 and 1924:
Page 1925 and 1926:
Page 1927 and 1928:
The format of an instruction in FPI
Page 1929 and 1930:
B.7 Version 1 of the Common VFP sub
Page 1931 and 1932:
Appendix C Legacy Instruction Mnemo
Page 1933 and 1934:
C.2 Pre-UAL pseudo-instruction NOP
Page 1935 and 1936:
Appendix D Deprecated and Obsolete
Page 1937 and 1938:
D.1.7 Use of AP[2] = 1, AP[1:0] = 0
Page 1939 and 1940:
D.2 Deprecated terminology Deprecat
Page 1941 and 1942:
D.4 Semaphore instructions The ARM
Page 1943 and 1944:
D.6 Explicit use of the PC in ARM i
Page 1945 and 1946:
Appendix E Fast Context Switch Exte
Page 1947 and 1948:
E.2 Modified virtual addresses Fast
Page 1949 and 1950:
E.3 Debug and trace Fast Context Sw
Page 1951 and 1952:
Appendix F VFP Vector Operation Sup
Page 1953 and 1954:
F.2 Vector length and stride contro
Page 1955 and 1956:
F.3 VFP register banks The Advanced
Page 1957 and 1958:
F.4 VFP instruction type selection
Page 1959 and 1960:
Appendix G ARMv6 Differences This a
Page 1961 and 1962:
G.2 Application level register supp
Page 1963 and 1964:
next_instr_addr = PC - 2; BranchWri
Page 1965 and 1966:
ARMv6 Differences SWP must be word-
Page 1967 and 1968:
ARMv6 Differences ARM deprecates an
Page 1969 and 1970:
Note ARMv6 Differences This appendi
Page 1971 and 1972:
The SMC instruction is added as par
Page 1973 and 1974:
G.4.4 Different definition of some
Page 1975 and 1976:
The Saved Program Status Registers
Page 1977 and 1978:
Two fault status encodings are depr
Page 1979 and 1980:
Note ARMv6 Differences When an impl
Page 1981 and 1982:
Cache behavior at reset ARMv6 Diffe
Page 1983 and 1984:
Execute Never (XN) ARMv6 Difference
Page 1985 and 1986:
ARMv6 Differences 4KB or less do no
Page 1987 and 1988:
G.7 System Control coprocessor (CP1
Page 1989 and 1990:
G.7.2 Organization of CP15 register
Page 1991 and 1992:
ARMv6 Differences The TLB Type ID R
Page 1993 and 1994:
In a PMSAv6 implementation, the for
Page 1995 and 1996:
Note Before ARMv7, the DFAR was cal
Page 1997 and 1998:
c7, Cache Dirty Status Register (CD
Page 1999 and 2000:
Block transfer operations ARMv6 Dif
Page 2001 and 2002:
ARMv6 Differences The range operati
Page 2003 and 2004:
G.7.14 c9, Cache lockdown support A
Page 2005 and 2006:
c9, TCM Region Registers (DTCMRR an
Page 2007 and 2008:
ARMv6 Differences An attempt to acc
Page 2009 and 2010:
NS_DL, bit [0] ARMv6 Differences No
Page 2011 and 2012:
ARMv6 Differences Table G-14 shows
Page 2013 and 2014:
Appendix H ARMv4 and ARMv5 Differen
Page 2015 and 2016:
introduce: ARMv4 and ARMv5 Differen
Page 2017 and 2018:
ARMv4 and ARMv5 Differences Instruc
Page 2019 and 2020:
H.3.2 Endian support ARMv4 and ARMv
Page 2021 and 2022:
Examples ARMv4 and ARMv5 Difference
Page 2023 and 2024:
H.4 Instruction set support ARMv4 a
Page 2025 and 2026:
ARMv4 and ARMv5 Differences Table H
Page 2027 and 2028:
H.4.2 Thumb instruction set support
Page 2029 and 2030:
H.4.3 System level instruction set
Page 2031 and 2032:
The Saved Program Status Registers
Page 2033 and 2034:
H.6 System level memory model ARMv4
Page 2035 and 2036:
SCTLR a S R ARMv4 and ARMv5 Differe
Page 2037 and 2038:
Second level Coarse page table desc
Page 2039 and 2040:
Translation table walks An MVA and
Page 2041 and 2042:
ARMv4 and ARMv5 Differences access
Page 2043 and 2044:
H.7 System Control coprocessor (CP1
Page 2045 and 2046:
ARMv4 and ARMv5 Differences H.7.2 O
Page 2047 and 2048:
c0, Cache Type Register (CTR) ARMv4
Page 2049 and 2050:
Table H-14 shows how the size of th
Page 2051 and 2052:
c1, System Control Register (SCTLR)
Page 2053 and 2054:
ARMv4 and ARMv5 Differences If the
Page 2055 and 2056:
H.7.7 c2, c3, c5, and c6, PMSA supp
Page 2057 and 2058:
Bn, bit [n], for n = 0 to 7 Buffera
Page 2059 and 2060:
c6, Memory Region registers (DMRR0-
Page 2061 and 2062:
set to: ARMv4 and ARMv5 Differences
Page 2063 and 2064:
Level 2 cache support ARMv4 and ARM
Page 2065 and 2066:
Register or operation General condi
Page 2067 and 2068:
ARMv4 and ARMv5 Differences If a da
Page 2069 and 2070:
ARMv4 and ARMv5 Differences 6. Writ
Page 2071 and 2072:
H.7.12 c9, TCM support ARMv4 and AR
Page 2073 and 2074:
TLB lockdown procedure, using the b
Page 2075 and 2076:
The translate and lock model ARMv4
Page 2077 and 2078:
Appendix I Pseudocode Definition Th
Page 2079 and 2080:
Pseudocode Definition In a few case
Page 2081 and 2082:
I.3 Data types This section describ
Page 2083 and 2084:
I.3.7 Lists Pseudocode Definition A
Page 2085 and 2086:
I.4 Expressions This section descri
Page 2087 and 2088:
I.5 Operators and built-in function
Page 2089 and 2090:
Pseudocode Definition Encoding diag
Page 2091 and 2092:
Unary plus, minus and absolute valu
Page 2093 and 2094:
I.6 Statements and program structur
Page 2095 and 2096:
I.6.2 Compound statements Pseudocod
Page 2097 and 2098:
Pseudocode Definition If has a bit
Page 2099 and 2100:
I.7.6 Coproc_DoneLoading() This fun
Page 2101 and 2102:
I.7.21 Hint_PreloadData() This proc
Page 2103 and 2104:
Appendix J Pseudocode Index This ap
Page 2105 and 2106:
Operator Meaning See Pseudocode Ind
Page 2107 and 2108:
Operator Meaning See return Procedu
Page 2109 and 2110:
BadMode() Test whether mode number
Page 2111 and 2112:
Coproc_SendLoadedWord() Send next l
Page 2113 and 2114:
FPCompareGE() Floating-point test f
Page 2115 and 2116:
GenerateIntegerZeroDivide() Generat
Page 2117 and 2118:
Max() Maximum of integers or reals
Page 2119 and 2120:
Pseudocode Index SendEvent() Perfor
Page 2121 and 2122:
Pseudocode Index UnsignedRecipEstim
Page 2123 and 2124:
Appendix K Register Index This appe
Page 2125 and 2126:
Register In a Description, see Regi
Page 2127 and 2128:
Register In a Description, see Cont
Page 2129 and 2130:
Register In a Description, see DBGD
Page 2131 and 2132:
Register In a Description, see DCCM
Page 2133 and 2134:
Page 2135 and 2136:
Register In a Description, see ICR,
Page 2137 and 2138:
Page 2139 and 2140:
Register In a Description, see NMRR
Page 2141 and 2142:
Register In a Description, see SCR
Page 2143 and 2144:
Register In a Description, see Tran
Page 2145 and 2146:
Glossary Abort Is caused by an ille
Page 2147 and 2148:
Cache contention Is when the number
Page 2149 and 2150:
Glossary Exception Handles an event
Page 2151 and 2152:
Glossary Memory coherency Is the pr
Page 2153 and 2154:
Software can rely on the bit readin
Page 2155 and 2156:
Glossary Should-Be-Zero-or-Preserve
Page 2157 and 2158:
Glossary Unindexed addressing Means
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