ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
Barrier_instrs, bits [19:16]
Indicates the supported Barrier instructions in the ARM and Thumb instruction sets.
Permitted values are:
0b0000 None supported. Barrier operations are provided only as CP15 operations.
0b0001 Adds support for the DMB, DSB, and ISB barrier instructions.
If this field is set to a value other than 0b0000 then the L1 unified cache field, bits [23:20],
must be set to 0b0000.
SMC_instrs, bits [15:12]
Indicates the supported SMC instructions. Permitted values are:
0b0000 Not supported.
0b0001 Adds support for the SMC instruction.
Note
The SMC instruction was called the SMI instruction in previous versions of the ARM
architecture.
Writeback_instrs, bits [11:8]
Indicates the support for Writeback addressing modes. Permitted values are:
0b0000 Basic support. Only the LDM, STM, PUSH, POP, SRS, and RFE instructions support
writeback addressing modes. These instructions support all of their writeback
addressing modes.
0b0001 Adds support for all of the writeback addressing modes defined in ARMv7.
WithShifts_instrs, bits [7:4]
Indicates the support for instructions with shifts. Permitted values are:
0b0000 Nonzero shifts supported only in MOV and shift instructions.
0b0001 Adds support for shifts of loads and stores over the range LSL 0-3.
0b0011 As for 0b0001, and adds support for other constant shift options, both on
load/store and other instructions.
0b0100 As for 0b0011, and adds support for register-controlled shift options.
Note
In this field, the value of 0b0010 is reserved.
Additions to the basic support indicated by the 0b0000 field value only apply when
the encoding supports them. In particular, in the Thumb instruction set there is no
difference between the 0b0011 and 0b0100 levels of support.
MOV instructions with shift options are treated as ASR, LSL, LSR, ROR or RRX instructions,
as described in Data-processing instructions on page B5-20.
B5-32 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B