ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
the subsequent instruction, if the instruction that caused the exception has been emulated in the
exception handler.
The ARM architecture makes no requirement that exception return must be to any particular place in the
execution stream. However, the architecture does have a preferred exception return for each exception other
than Reset. The values of the SPSR.IT[7:0] bits generated on exception entry are always correct for the
preferred exception return, but might require adjustment by software if returning elsewhere.
In some cases, the value of the LR set on taking the exception, as shown in Table B1-4 on page B1-34,
makes it necessary to perform a subtraction to calculate the appropriate return address. The value that must
be subtracted for the preferred exception return, and other details of the preferred exception return, are given
in the description of each of the exceptions.
The ARM architecture provides the following exception return instructions:
Data-processing instructions with the S bit set and the PC as a destination, see SUBS PC, LR and
related instructions on page B6-25.
Typically, SUBS is used when a subtraction is required, and SUBS with an operand of 0 or MOVS is used
otherwise.
From ARMv6, the RFE instruction, see RFE on page B6-16. If a subtraction is required, typically it is
performed before saving the LR value to memory.
In ARM state, a form of the LDM instruction, see LDM (exception return) on page B6-5. If a
subtraction is required, typically it is performed before saving the LR value to memory.
Alignment of exception returns
An unaligned exception return is one where the address transferred to the PC on an exception return is not
aligned to the size of instructions in the target instruction set. The target instruction set is controlled by the
[J,T] bits of the value transferred to the CPSR for the exception return. The behavior of the hardware for
exception returns for different values of the [J,T] bits is as follows:
[J,T] == 00 The target instruction set state is ARM state. Bits [1:0] of the address transferred to the PC
are ignored by the hardware.
[J,T] == 01 The target instruction set state is Thumb state:
bit [0] of the address transferred to the PC is ignored by the hardware
bit [1] of the address transferred to the PC is part of the instruction address.
[J,T] == 10 The target instruction set state is Jazelle state. In a non-trivial implementation of the Jazelle
extension, bits [1:0] of the address transferred to the PC are part of the instruction address.
In a trivial implementation of the Jazelle extension, behavior is UNPREDICTABLE, see
Exception return to an unsupported instruction set state on page B1-40. For details of the
trivial implementation of Jazelle state see Trivial implementation of the Jazelle extension on
page B1-81.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-39