ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
Reading a Format A register returns the value last written to it.
Writing a Format A register has the following effects:
The next cache miss in each cache set replaces the cache line with the specified WAY in that cache set.
The replacement strategy for the cache is constrained so that it can only select cache lines with the
specified WAY and higher until the register is written again.
The format of a Format B lockdown register is:
31 30 W W–1 0
L UNK/SBZ WAY
Reading a Format B register returns the value last written to it.
Writing a Format B register has the following effects:
If L == 1, all cache misses replace the cache line with the specified WAY in the relevant cache set
until the register is written again.
If L ==0:
— If the previous value of L was 0, and the previous value of WAY is smaller than the new value,
the behavior is UNPREDICTABLE.
— If the previous value of L was not 0, the replacement strategy for the cache is constrained so
that it can only select cache lines with the specified WAY and higher until the register is written
again.
Format A and B cache lockdown procedure
The procedure for locking down N lockdown blocks is as follows:
1. Ensure that no processor exceptions can occur during the execution of this procedure, for example by
disabling interrupts. If for some reason this is not possible, all code and data used by any exception
handlers that can get called must be treated as code and data used by this procedure for the purpose
of steps 2 and 3.
2. If an instruction cache or a unified cache is being locked down, ensure that all the code executed by
this procedure is in an Non-cacheable area of memory.
3. If a data cache or a unified cache is being locked down, ensure that all data used by the following
code is in an Non-cacheable area of memory, apart from the data that is to be locked down.
4. Ensure that the data or instructions that are to be locked down are in a Cacheable area of memory.
5. Ensure that the data or instructions that are to be locked down are not already in the cache, using
cache clean, invalidate, or clean and invalidate instructions as appropriate.
6. For each value of i from 0 to N-1:
a. Write to the CP15 c9 register with:
WAY == i, for Formats A and B
L == 1, for Format B only.
b. For each of the cache lines to be locked down in lockdown block i:
AppxH-54 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B