05.02.2013 Views

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

H.3.2 Endian support<br />

<strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 Differences<br />

<strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5 support big <strong>and</strong> little endian operation. Little endian support is consistent with<br />

<strong>ARM</strong>v7. Big endian control, configuration, <strong>and</strong> the connectivity of data bytes between the <strong>ARM</strong> register<br />

file <strong>and</strong> memory is different. However, the difference is only visible when communicating between big<br />

endian <strong>and</strong> little endian agents using memory. The agents can be different processors or programs running<br />

with different endianness settings on the same processor.<br />

For <strong>ARM</strong>v4 <strong>and</strong> <strong>ARM</strong>v5, the distinction between big endian memory <strong>and</strong> little endian memory is managed<br />

by changing the addresses of the bytes in a word. For <strong>ARM</strong>v7, the distinction between big endian memory<br />

<strong>and</strong> little endian memory is managed by keeping the byte addresses the same, <strong>and</strong> reordering the bytes in<br />

the halfword or word. The endian formats are:<br />

LE Little endian format used by <strong>ARM</strong>v4, <strong>ARM</strong>v5, <strong>ARM</strong>v6, <strong>and</strong> <strong>ARM</strong>v7<br />

BE Big endian format used by <strong>ARM</strong>v6 (endianness controlled by the SETEND instruction) <strong>and</strong><br />

<strong>ARM</strong>v7<br />

BE-32 Big endian format used by <strong>ARM</strong>v4, <strong>ARM</strong>v5, <strong>and</strong> <strong>ARM</strong>v6 (legacy format, endianness<br />

controlled by the SCTLR.B bit).<br />

Table H-1 shows how the addresses of bytes are changed in the BE-32 endian format. In this table, A is a<br />

doubleword-aligned address <strong>and</strong> S, T, U, V, W, X, Y, Z are the bytes at addresses A to A+7 in the <strong>ARM</strong>v7<br />

memory map.<br />

Table H-1 Addresses of bytes in endian formats<br />

Byte Address in format BE or LE Address in format BE-32<br />

S A A+3<br />

T A+1 A+2<br />

U A+2 A+1<br />

V A+3 A<br />

W A+4 A+7<br />

X A+5 A+6<br />

Y A+6 A+5<br />

Z A+7 A+4<br />

Aligned memory accesses are performed using these byte addresses as shown in Table A3-4 on page A3-8<br />

for the LE endian format <strong>and</strong> in Table A3-3 on page A3-7 for the BE <strong>and</strong> BE-32 formats, in each case<br />

extended consistently to doubleword accesses. Table H-2 on page AppxH-8 shows which bytes are accessed<br />

by each type of aligned memory access <strong>and</strong> the significance order in which they are accessed.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. AppxH-7

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!