ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Thumb Instruction Set Encoding
If the destination register specifier of an LDRB, LDRH, LDRSB, or LDRSH instruction is 0b1111, the
instruction is a memory hint instead of a load operation.
If the destination register specifier of an MRC instruction is 0b1111, bits [31:28] of the value
transferred from the coprocessor are written to the N, Z, C, and V flags in the APSR, and bits [27:0]
are discarded.
A6.1.3 Use of 0b1101 as a register specifier
R13 is defined in the Thumb instruction set so that its use is primarily as a stack pointer, and R13 is normally
identified as SP in Thumb instructions. In 32-bit Thumb instructions, if you use R13 as a general-purpose
register beyond the architecturally defined constraints described in this section, the results are
UNPREDICTABLE.
The restrictions applicable to R13 are described in:
R13[1:0] definition
32-bit Thumb instruction support for R13.
See also 16-bit Thumb instruction support for R13 on page A6-5.
R13[1:0] definition
Bits [1:0] of R13 are SBZP. Writing a nonzero value to bits [1:0] causes UNPREDICTABLE behavior.
32-bit Thumb instruction support for R13
R13 instruction support is restricted to the following:
R13 as the source or destination register of a MOV instruction. Only register to register transfers without
shifts are supported, with no flag setting:
MOV SP,
MOV ,SP
Using the following instructions to adjust R13 up or down by a multiple of 4:
ADD{W} SP,SP,#
SUB{W} SP,SP,#
ADD SP,SP,
ADD SP,SP,,LSL # ; For = 1,2,3
SUB SP,SP,
SUB SP,SP,,LSL # ; For = 1,2,3
R13 as a base register of any load/store instruction. This supports SP-based addressing for load,
store, or memory hint instructions, with positive or negative offsets, with and without writeback.
R13 as the first operand in any ADD{S}, CMN, CMP, or SUB{S} instruction. The add and subtract
instructions support SP-based address generation, with the address going into a general-purpose
register. CMN and CMP are useful for stack checking in some circumstances.
R13 as the transferred register in any LDR or STR instruction.
A6-4 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B