ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.12.28 CP15 c5, Fault status registers
Virtual Memory System Architecture (VMSA)
There are two fault status registers, in CP15 c5, and the architecture provides encodings for two additional
IMPLEMENTATION DEFINED registers. Table B3-30 summarizes these registers.
Register name Description
Data Fault Status Register (DFSR) c5, Data Fault Status Register (DFSR)
Fault information is returned using the fault status registers and the fault address registers described in CP15
c6, Fault Address registers on page B3-124. For details of how these registers are used see Fault Status and
Fault Address registers in a VMSA implementation on page B3-48.
c5, Data Fault Status Register (DFSR)
The Data Fault Status Register, DFSR, holds status information about the last data fault.
The DFSR is:
a 32-bit read/write register
accessible only in privileged modes
when the Security Extensions are implemented, a Banked register.
The format of the DFSR is:
Bits [31:13,9:8]
UNK/SBZP.
ExT, bit [12] External abort type. This bit can be used to provide an IMPLEMENTATION DEFINED
classification of external aborts.
For aborts other than external aborts this bit always returns 0.
Table B3-30 Fault status registers
Instruction Fault Status Register (IFSR) c5, Instruction Fault Status Register (IFSR) on page B3-122
Auxiliary Data Fault Status Register (ADFSR)
Auxiliary Instruction Fault Status Register (AIFSR)
c5, Auxiliary Data and Instruction Fault Status Registers
(ADFSR and AIFSR) on page B3-123
31 13
12 11 10 9 8 7 4 3 0
UNK/SBZP
(0) (0) Domain FS[3:0]
ExT
WnR
FS[4]
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-121