ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
C6.6.3 CP14 debug registers access permissions
By default, certain CP14 debug registers can be accessed from User mode. However, the processor can be
programmed to prevent User mode access to these CP14 debug registers. For more information, see the
description of the UDCCdis bit in Debug Status and Control Register (DBGDSCR) on page C10-10.
All CP14 debug registers can be accessed if the processor is in Debug state.
Note
When the Software Lock (DBGLAR) is implemented for a memory-mapped interface, it does not affect the
behavior of CP14 instructions.
Baseline CP14 debug registers access permissions
Access to the Baseline CP14 debug registers is governed by the processor mode, Debug state and the value
of DBGDSCR.UDCCdis. In addition, when the OS Lock is set accesses to the baseline registers are
UNPREDICTABLE.
Note
OS Lock is implemented only in v7 Debug.
These access permissions are shown:
in Table C6-8 for v6 Debug and v6.1 Debug
in Table C6-9 on page C6-37 for v7 Debug
Table C6-8 Access to Baseline CP14 debug registers in v6 Debug and v6.1 Debug
Conditions
Debug state Processor mode DBGDSCR.UDCCdis b
Baseline CP14
instructions a
DBGDSCRint
writes
Yes X X Proceed Proceed
No User 0 Proceed UNDEFINED
No User 1 UNDEFINED UNDEFINED
No Privileged X Proceed Proceed
a. Read DBGDIDR, DBGDSCRint, DBGDTRRXint, or write DBGDTRTXint.
Attempting to use an MCR instruction to access the DBGDIDR always causes an Undefined Instruction exception.
b. DCC User mode accesses disable bit, see Debug Status and Control Register (DBGDSCR) on page C10-10.
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