ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
PUSH Standard syntax
STMDB SP!, Equivalent STM syntax
where:
See Standard assembler syntax fields on page A8-7.
Instruction Details
Is a list of one or more registers to be stored, separated by commas and surrounded by
{ and }. The lowest-numbered register is stored to the lowest memory address, through to
the highest-numbered register to the highest memory address.
If the list contains more than one register, the instruction is assembled to encoding T1, T2,
or A1. If the list contains exactly one register, the instruction is assembled to encoding T1,
T3, or A2.
The SP and PC can be in the list in ARM code, but not in Thumb code. However, ARM
instructions that include the SP or the PC in the list are deprecated, and if the SP is in the
list, the value the instruction stores for the SP is UNKNOWN.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); NullCheckIfThumbEE(13);
address = SP - 4*BitCount(registers);
for i = 0 to 14
if registers == ‘1’ then
if i == 13 && i != LowestSetBit(registers) then // Only possible for encoding A1
MemA[address,4] = bits(32) UNKNOWN;
else
MemA[address,4] = R[i];
address = address + 4;
if registers == ‘1’ then // Only possible for encoding A1 or A2
MemA[address,4] = PCStoreValue();
SP = SP - 4*BitCount(registers);
Exceptions
Data Abort.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-249