ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
HALTED, bit [0]
Processor Halted bit. The possible values of this bit are:
0 The processor is in Non-debug state.
1 The processor is in Debug state.
Note
Between receiving a restart request and restarting Non-debug state operation,
the processor is in Debug state and this bit reads as 1
After programming a debug event, the external debugger can poll this bit until it is set to 1.
At that point it knows that the processor has entered Debug state.
See Chapter C5 Debug State for a definition of Debug state.
Table C10-1 shows the access to each field of the DBGDSCR, and the reset value of each field. It also shows
the Debug architecture versions in which each field is defined.
Table C10-1 DBGDSCR bit access and reset values
Bits Field name Version Access a Reset value b
[31] - - UNK/SBZP -
[30] RXfull All Read-only 0
[29] TXfull All Read-only 0
[28] - - UNK/SBZP -
[27] RXfull_l v7 Debug Read-only 0
[26] TXfull_l v7 Debug Read-only 0
[25] PipeAdv v7 Debug Read-only UNKNOWN
[24] InstrCompl_l v7 Debug Read-only UNKNOWN
[23:22] - - UNK/SBZP -
[21:20] ExtDCCmode v7 Debug Read/write 00
[19] ADAdiscard v6.1 Debug, v7 Debug Read-only or
Read/write c
[18] NS v6.1 Debug, v7 Debug Read-only f
[17] SPNIDdis v6.1 Debug, v7 Debug Read-only f
[16] SPIDdis v6.1 Debug, v7 Debug Read-only f
[15] MDBGen All RWInt 0
C10-20 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
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