ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VREV. , Encoded as Q = 1
VREV. , Encoded as Q = 0
where:
Instruction Details
The size of the regions in which the vector elements are reversed. It must be one of:
16 encoded as op = 0b10
32 encoded as op = 0b01
64 encoded as op = 0b00.
See Standard assembler syntax fields on page A8-7. An ARM VREV instruction must be
unconditional.
The size of the vector elements. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10.
must specify a smaller size than .
, The destination vector and the operand vector, for a quadword operation.
, The destination vector and the operand vector, for a doubleword operation.
If op + size >= 3, the instruction is reserved.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
bits(64) dest;
for r = 0 to regs-1
for e = 0 to elements-1
// Calculate destination element index by bitwise EOR on source element index:
e_bits = e; d_bits = e_bits EOR reverse_mask; d = UInt(d_bits);
Elem[dest,d,esize] = Elem[D[m+r],e,esize];
D[d+r] = dest;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-733