ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
If CPSR.I == 0 and SCTLR.FI == 1, IRQ exceptions can be taken. In this case IRQ exception entry
is precise to an instruction boundary, except that some of the effects of the instruction that follows
that boundary might have occurred. These effects are restricted to those that can be repeated
idempotently and without breaking the rules in Single-copy atomicity on page A3-27. Examples of
such effects are:
— changing the value of a register that the instruction writes but does not read
— performing an access to Normal memory.
Note
This relaxation of the normal definition of a precise asynchronous exception permits interrupts to
occur during the execution of instructions that change register or memory values, while only
requiring the implementation to restore those register values that are needed to correctly re-execute
the instruction after the preferred exception return. LDM and STM are examples of such instructions.
The following pseudocode describes how this exception is taken:
// TakeIRQException()
// ==================
TakeIRQException()
// Determine return information. SPSR is to be the current CPSR, and LR is to be the
// current PC minus 0 for Thumb or 4 for ARM, to change the PC offsets of 4 or 8
// respectively from the address of the current instruction into the required address
// of the instruction boundary at which the interrupt occurred plus 4. For this
// purpose, the PC and CPSR are considered to have already moved on to their values
// for the instruction following that boundary.
new_lr_value = if CPSR.T == ‘1’ then PC else PC-4;
new_spsr_value = CPSR;
// Determine whether IRQs are trapped to Monitor mode.
trap_to_monitor = HaveSecurityExt() && SCR.IRQ == ‘1’;
// Enter IRQ (‘10010’) or Monitor (‘10110’) mode, and ensure Secure state if initially
// in Monitor mode. This affects the banked versions of various registers accessed
// later in the code.
if CPSR.M == ‘10110’ then SCR.NS = ‘0’;
CPSR.M = if trap_to_monitor then ‘10110’ else ‘10010’;
// Write return information to registers, and make further CPSR changes: IRQs disabled,
// other interrupts disabled if appropriate, IT state reset, instruction set and
// endianness to SCTLR-configured values.
SPSR[] = new_spsr_value;
R[14] = new_lr_value;
CPSR.I = ‘1’;
if trap_to_monitor then
CPSR.F = ‘1’; CPSR.A = ‘1’;
else
if !HaveSecurityExt() || SCR.NS == ‘0’ || SCR.AW == ‘1’ then CPSR.A = ‘1’;
CPSR.IT = ‘00000000’;
CPSR.J = ‘0’; CPSR.T = SCTLR.TE; // TE=0: ARM, TE=1: Thumb
CPSR.E = SCTLR.EE; // EE=0: little-endian, EE=1: big-endian
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