ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
Accessing the ID_DFR0
To access the ID_DFR0 you read the CP15 registers with set to 0, set to c0, set to c1, and
set to 2. For example:
MRC p15, 0, , c0, c1, 2 ; Read Debug Feature Register 0
B5.2.3 c0, Auxiliary Feature Register 0 (ID_AFR0)
The Auxiliary Feature Register 0, ID_AFR0, provides information about the IMPLEMENTATION DEFINED
features of the processor.
The format of the ID_AFR0 is:
31 16 15 12 11 8 7 4 3 0
Reserved, RAZ
Bits [31:16] Reserved, RAZ.
IMPLEMENTATION DEFINED, bits [15:12]
IMPLEMENTATION DEFINED, bits [11:8]
IMPLEMENTATION DEFINED, bits [7:4]
IMPLEMENTATION DEFINED, bits [3:0]
The Auxiliary Feature Register 0 has four 4-bit IMPLEMENTATION FIELDS. These fields are defined by the
implementer of the design. The implementer is identified by the Implementer field of the Main ID Register,
see:
c0, Main ID Register (MIDR) on page B3-81, for a VMSA implementation
c0, Main ID Register (MIDR) on page B4-32, for a PMSA implementation.
The Auxiliary Feature Register 0 enables implementers to include additional design features in the CPUID
scheme. Field definitions for the Auxiliary Feature Register 0 might:
differ between different implementers
be subject to change
migrate over time, for example if they are incorporated into the main architecture.
Accessing the ID_AFR0
To access the ID_AFR0 you read the CP15 registers with set to 0, set to c0, set to c1, and
set to 3. For example:
MRC p15, 0, , c0, c1, 3 ; Read Auxiliary Feature Register 0
IMP IMP IMP IMP
B5-8 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B