ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
G.7.10 c7, Cache operations
Table G-7 shows the cache operations defined for ARMv6. They are performed as MCR instructions and only
operate on a level 1 cache associated with a specific processor. The equivalent operations in ARMv7 operate
on multiple levels of cache. See CP15 c7, Cache maintenance and other functions on page B3-126. For a
list of required operations in ARMv6, see Cache support on page AppxG-21. Support of additional
operations is IMPLEMENTATION DEFINED.
Table G-7 Cache operation support
Operation CRn opc1 CRm opc2
Invalidate instruction cache a c7 0 c5 0
Invalidate instruction cache line by MVA a c7 0 c5 1
Invalidate instruction cache line by set/way c7 0 c5 2
Flush entire branch predictor array a c7 0 c5 6
Flush branch predictor array entry by MVA a c7 0 c5 7
Invalidate data cache c7 0 c6 0
Invalidate data cache line by MVA a c7 0 c6 1
Invalidate data cache line by set/way a c7 0 c6 2
Invalidate unified cache, or instruction cache and data cache c7 0 c7 0
Invalidate unified cache line by MVA c7 0 c7 1
Invalidate unified cache line by set/way c7 0 c7 2
Clean data cache c7 0 c10 0
Clean data cache line by MVA a c7 0 c10 1
Clean data cache line by set/way a c7 0 c10 2
Test and Clean data cache b c7 0 c10 3
Cache Dirty Status Register c c7 0 c10 6
Clean entire unified cache c7 0 c11 0
Clean unified cache line by MVA a c7 0 c11 1
Clean unified cache line by set/way c7 0 c11 2
Prefetch instruction cache line by MVA d c7 0 c13 1
AppxG-38 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B