ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VSRA. {,} , # Encoded as Q = 1
VSRA. {,} , # Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VSRA instruction must be
unconditional.
The data type for the elements of the vectors. It must be one of:
S signed, encoded as U = 0
U unsigned, encoded as U = 1.
The data size for the elements of the vectors. It must be one of:
8 Encoded as L = ’0’, imm6 = ’001’. (8– ) is encoded in imm6.
16 Encoded as L = ’0’, imm6 = ’01’. (16 – ) is encoded in imm6.
32 Encoded as L = ’0’, imm6 = ’1’. (32 – ) is encoded in imm6.
64 Encoded as L = ’1’. (64 – ) is encoded in imm6.
, The destination vector, and the operand vector, for a quadword operation.
, The destination vector, and the operand vector, for a doubleword operation.
The immediate value, in the range 1 to . See the description of for how
is encoded.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
result = Int(Elem[D[m+r],e,esize], unsigned) >> shift_amount;
Elem[D[d+r],e,esize] = Elem[D[d+r],e,esize] + result;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-765