ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

OS Save and Restore registers, and Device Power-down and Reset registers
Debug Register Interfaces
No error response returned on read or write accesses when the core power domain is
powered down. However, accesses to the OS Lock Access Register (DBGOSLAR) and OS
Save and Restore Register (DBGOSSRR) are UNPREDICTABLE when the core power domain
is powered-down.
All of the management registers, except for the IMPLEMENTATION DEFINED integration registers
The management registers are registers 823 - 1023, in the address range 0xD00-0xFFC.
Requiring all these registers to be in the debug power domain simplifies the decoding of
register addresses for the registers in the debug power domain.
Note
The CP15 c0 registers (0xD00-0xDFC) are included in this category.
For all other registers, including any IMPLEMENTATION DEFINED registers, it is IMPLEMENTATION DEFINED
whether the register is implemented in the core or the debug power domain.
Processor
Figure C6-1 shows the recommended power domain split.
Remainder of
processor logic
All other
Debug registers
Bridge
External
debug
interface
DBGDIDR, DBGECR, DBGDRCR,
OS Save and Restore registers,
DBGPRCR, DBGPRSR, and
Management registers
Core
power domain
Core domain Vdd
Debug domain Vdd
DBGPWRDUP
DBGNOPWRDWN
Debug
power domain
Power
controller
Power domain boundary
Figure C6-1 Recommended power domain split between core and debug power domains
The signals DBGNOPWRDWN and DBGPWRDUP shown in Figure C6-1 above form an interface
between the power controller and the processor debug logic that is in the debug power domain. With this
interface:
the external debugger can request the power controller to emulate power-down, simplifying the
requirements on software by sacrificing entirely realistic behavior
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C6-7