ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Application Level Memory Model
Memory type
attribute
Device Shareable - Intended to handle memory-
mapped peripherals that are
shared by several processors.
Non-
shareable
Normal Outer
Shareable
Inner
Shareable
Non-
shareable
A3.5.3 Atomicity in the ARM architecture
- Intended to handle memory-
mapped peripherals that are
used only by a single processor.
Cacheability, one of: a The Outer Shareable attribute
Non-cacheable
Write-Through Cacheable
Write-Back Write-Allocate Cacheable
Write-Back no Write-Allocate Cacheable
qualifies the Shareable attribute
for Normal memory regions
and enables two levels of
Normal memory sharing. b
Cacheability, one of: a Intended to handle Normal
Non-cacheable
Write-Through Cacheable
Write-Back Write-Allocate Cacheable
Write-Back no Write-Allocate Cacheable
memory that is shared between
several processors.
Cacheability, one of: a Intended to handle Normal
Non-cacheable
Write-Through Cacheable
Write-Back Write-Allocate Cacheable
Write-Back no Write-Allocate Cacheable
a. The cacheability attribute is defined independently for inner and outer cache regions.
b. The significance of the Outer Shareable attribute is IMPLEMENTATION DEFINED.
Table A3-8 Memory attribute summary (continued)
Shareability Other attributes Description
memory that is used by only a
single processor.
Atomicity is a feature of memory accesses, described as atomic accesses. The ARM architecture description
refers to two types of atomicity, defined in:
Single-copy atomicity on page A3-27
Multi-copy atomicity on page A3-28.
A3-26 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B