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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Assembler syntax<br />

TST , {,}<br />

where:<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7.<br />

The first oper<strong>and</strong> register.<br />

The register that is optionally shifted <strong>and</strong> used as the second oper<strong>and</strong>.<br />

Instruction Details<br />

The shift to apply to the value read from . If present, encoding T1 is not permitted. If<br />

absent, no shift is applied <strong>and</strong> all encodings are permitted. Shifts applied to a register on<br />

page A8-10 describes the shifts <strong>and</strong> how they are encoded.<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations();<br />

(shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);<br />

result = R[n] AND shifted;<br />

APSR.N = result;<br />

APSR.Z = IsZeroBit(result);<br />

APSR.C = carry;<br />

// APSR.V unchanged<br />

Exceptions<br />

None.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A8-457

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