ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
c0, Instruction Set Attribute Register 0 (ID_ISAR0)
The format of the ID_ISAR0 is:
31 28 27 24 23 20 19
16 15 12 11 8 7 4 3 0
Reserved,
RAZ
Divide
_instrs
Bits [31:28] Reserved, RAZ.
Divide_instrs, bits [27:24]
Debug_instrs, bits [23:20]
Coproc_instrs, bits [19:16]
Debug
_instrs
Coproc
_instrs
CmpBranch
_instrs
Bitfield
_instrs
Indicates the supported Divide instructions. Permitted values are:
0b0000 . None supported.
0b0001 . Adds support for SDIV and UDIV.
Indicates the supported Debug instructions. Permitted values are:
0b0000 None supported.
0b0001 Adds support for BKPT.
Indicates the supported Coprocessor instructions. Permitted values are:
0b0000 None supported, except for separately attributed architectures including CP15,
CP14, and Advanced SIMD and VFP.
0b0001 Adds support for generic CDP, LDC, MCR, MRC, and STC.
0b0010 As for 0b0001, and adds generic CDP2, LDC2, MCR2, MRC2, and STC2.
0b0011 As for 0b0010, and adds generic MCRR and MRRC.
0b0100 As for 0b0011, and adds generic MCRR2 and MRRC2.
CmpBranch_instrs, bits [15:12]
Indicates the supported combined Compare and Branch instructions in the Thumb
instruction set. Permitted values are:
0b0000 None supported.
0b0001 Adds support for CBNZ and CBZ.
Bitfield_instrs, bits [11:8]
Indicates the supported BitField instructions. Permitted values are:
0b0000 None supported.
0b0001 Adds support for BFC, BFI, SBFX, and UBFX.
BitCount
_instrs
BitCount_instrs, bits [7:4]
Indicates the supported Bit Counting instructions. Permitted values are:
0b0000 None supported.
0b0001 Adds support for CLZ.
Swap
_instrs
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