ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
C6.2.4 Recommended reset scheme for v7 Debug
The processor reset scheme is IMPLEMENTATION DEFINED. The ARM architecture, described in parts A and
B of this manual, does not distinguish different levels of reset. However, in a typical system, there are a
number of reasons why multiple levels of reset might exist. In particular, for debug:
It is desirable to be able to debug the reset sequence. This requires support for:
— setting the debug register values before performing a processor reset
— a processor reset not resetting the debug register values.
Providing separate power domains means you might need to reset the debug logic independently from
the logic in the core power domain.
For these reasons, v7 Debug introduces a distinction between debug logic reset and non-debug logic reset.
These resets can be applied independently. The reset descriptions in parts A and B of this manual describe
the non-debug logic reset. Part C describes the debug logic reset and its interaction with the non-debug logic
reset. The non-debug logic reset is sometimes referred to as a core logic reset.
ARM recommends use of the following reset signals for an implementation that supports these independent
resets:
nSYSPORESET This signal must be driven LOW on power-up of both the core and debug power
domains. It sets parts of the processor logic, including debug logic, to a known state.
nCOREPORESET If the core power domain is powered down while the system is still powered up, this
signal must be driven LOW when the core power domain is powered back up. It sets
parts of the processor logic in the core power domain to a known state. Also, this
reset initializes the debug registers that are in the core power domain.
nRESET This signal is driven LOW to generate a warm reset, that is, when the system wants
to set the processor to a known state but the reset has nothing to do with any
power-down, for example a watchdog reset. It sets parts of the non-debug processor
logic to a known state. A debug session must be unaffected by this reset.
PRESETDBGn The debugger drives this signal LOW to set parts of the debug logic to a known state.
This signal must be driven LOW on power-up of the debug logic.
v6 Debug and v6.1 Debug systems do not support multiple power domains and therefore ARM recommends
a less flexible reset scheme, consisting of only nSYSPORESET and nRESET. The debug logic is reset
only on nSYSPORESET and has no independent reset signal.
In the v7 Debug recommended reset scheme, a separate PRESETDBGn reset signal can be asserted at any
time, not just at power-up. This new signal has similar effects to nSYSPORESET, that is, it clears all debug
registers, unless otherwise noted by the register definition. For more information, see Appendix A
Recommended External Debug Interface.
Asynchronously asserting PRESETDBGn can lead to UNPREDICTABLE behavior. For example, the reset
might change the values of debug registers that are in use or will be used by software.
For more information about this reset scheme, contact ARM.
C6-16 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B