ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A4.10 Coprocessor instructions
The Instruction Sets
There are three types of instruction for communicating with coprocessors. These permit the processor to:
Initiate a coprocessor data-processing operation. For details see CDP, CDP2 on page A8-68.
Transfer general-purpose registers to and from coprocessor registers. For details, see:
— MCR, MCR2 on page A8-186
— MCRR, MCRR2 on page A8-188
— MRC, MRC2 on page A8-202
— MRRC, MRRC2 on page A8-204.
Load or store the values of coprocessor registers. For details, see:
— LDC, LDC2 (immediate) on page A8-106
— LDC, LDC2 (literal) on page A8-108
— STC, STC2 on page A8-372.
The instruction set distinguishes up to 16 coprocessors with a 4-bit field in each coprocessor instruction, so
each coprocessor is assigned a particular number.
Note
One coprocessor can use more than one of the 16 numbers if a large coprocessor instruction set is required.
Coprocessors 10 and 11 are used, together, for VFP and some Advanced SIMD functionality. There are
different instructions for accessing these coprocessors, of similar types to the instructions for the other
coprocessors, that is, to:
Initiate a coprocessor data-processing operation. For details see VFP data-processing instructions on
page A4-38.
Transfer general-purpose registers to and from coprocessor registers. For details, see Advanced SIMD
and VFP register transfer instructions on page A4-29.
Load or store the values of coprocessor registers. For details, see Advanced SIMD and VFP load/store
instructions on page A4-26.
Coprocessors execute the same instruction stream as the processor, ignoring non-coprocessor instructions
and coprocessor instructions for other coprocessors. Coprocessor instructions that cannot be executed by
any coprocessor hardware cause an Undefined Instruction exception.
For more information about specific coprocessors see Coprocessor support on page A2-68.
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