ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common Memory System Architecture Features
; Enter this code with containing the new 32-bit instruction. Use STRH in the first
; line instead of STR for a 16-bit instruction.
STR , [instruction location]
Clean data cache by MVA to point of unification [instruction location]
DSB ; Ensures visibility of the data cleaned from the data cache
Invalidate instruction cache by MVA [instruction location]
Invalidate BTC entry by MVA [instruction location]
DSB ; Ensures completion of the instruction cache invalidation
ISB
B2.2.8 Multiprocessor effects on cache maintenance operations
This section describes the multiprocessor effects on cache maintenance operations for the base ARMv7
architecture and the base ARMv7 architecture with Multiprocessing Extensions.
Base ARMv7 architecture
The base ARMv7 architecture defines that all cache maintenance operations apply only to the caches
directly attached to the processor on which the operation is executed. There is no requirement that cache
maintenance operations influence all processors with which the data can be shared.
In porting an architecturally portable multiprocessor operating system to ARMv7, when a cache
maintenance operation is performed, Inter-Processor Interrupts (IPIs) must be used to inform other
processors in a multiprocessor configuration that they must perform the equivalent operation.
Multiprocessing Extensions
To improve the implementation of multiprocessor systems, a set of extensions to ARMv7, called the
Multiprocessing Extensions, has been introduced. These expand the role of cache and branch predictor
maintenance operations in the multiprocessing system. For the VMSA architecture, the Multiprocessing
Extensions also extend the role of TLB operations. For more information see Multiprocessor effects on TLB
maintenance operations on page B3-62.
The extensions can be implemented in a uniprocessor system with no hardware support for cache coherency.
In such a system, the Inner Shareable and Outer Shareable domains would be limited to being the single
processor, and all instructions defined to apply to the Inner Shareable domains behave as aliases of the local
operations.
Data and Unified cache operations to the point of coherency
The following instructions have an effect on data and unified caches to the point of coherency, and must
affect the caches of other processors in the shareability domain described by the shareability attributes of
the MVA passed with the instruction:
invalidate data, or unified, cache line by MVA to the point of coherency (DCIMVAC)
clean data, or unified, cache line by MVA to the point of coherency (DCCMVAC)
clean and invalidate data (or unified) cache line by MVA to the point of coherency (DCCIMVAC).
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