ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VSHRN.I , , #
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VSHRN instruction must be
unconditional.
The data size for the elements of the vectors. It must be one of:
16 Encoded as imm6 = ’001’. (8 – ) is encoded in imm6.
32 Encoded as imm6 = ’01’. (16 – ) is encoded in imm6.
64 Encoded as imm6 = ’1’. (32 – ) is encoded in imm6.
, The destination vector, and the operand vector.
The immediate value, in the range 1 to /2. See the description of for how
is encoded.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for e = 0 to elements-1
result = LSR(Elem[Q[m>>1],e,2*esize], shift_amount);
Elem[D[d],e,esize] = result;
Exceptions
Undefined Instruction.
Pseudo-instructions
VSHRN.I , , #0 is a synonym for VMOVN.I ,
For details see VMOVN on page A8-656.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-759