ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VSHL. {,} , Encoded as Q = 1
VSHL. {,} , Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VSHL instruction must
be unconditional.
The data type for the elements of the vectors. It must be one of:
S signed, encoded as U = 0
U unsigned, encoded as U = 1.
The data size for the elements of the vectors. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10
64 encoded as size = 0b11.
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
shift = SInt(Elem[D[n+r],e,esize]);
result = Int(Elem[D[m+r],e,esize], unsigned)