ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Some individual registers can be made inaccessible by setting configuration bits, possibly including
IMPLEMENTATION DEFINED configuration bits, to disable access to the register. The effects of the
architecturally-defined configuration bits are defined individually in this manual. Typically, setting a
configuration bit to disable access to a register results in the register becoming UNDEFINED for MRC and MCR
accesses.
Effects of the Security Extensions
In Non-secure state, any User or privileged access to a CP15 register is UNDEFINED if either:
There are no circumstances in which all bits and fields in the register can be accessed from
Non-secure privileged modes.
Settings in the NSACR mean that there are no circumstances in which all bits and fields in the register
can be accessed from Non-secure privileged modes.
Note
The ARMv7-A architecture does not define any registers of this type. However an ARMv7-A
implementation might include one or more IMPLEMENTATION DEFINED registers of this type.
When Non-secure access to a field of a CP15 register is controlled by an access control bit in the NSACR,
and that access control bit is set to 0, then the controlled register field is RAZ/WI when accessed from a
privileged mode in Non-secure state. If the register can be accessed from User mode then the field is also
RAZ/WI when accessed from User mode.
If write access to a register is disabled by the CP15SDISABLE signal then any MCR access to that register
is UNDEFINED.
Reset behavior of CP15 registers
After a reset, only a limited subset of the processor state is guaranteed to be set to defined values. On reset,
the VMSAv7 architecture requires that the following CP15 registers are set to defined values.
Note
When the Security Extensions are implemented, only the Secure copy of a banked register is reset to the
defined value.
The SCTLR, see c1, System Control Register (SCTLR) on page B3-96.
The CPACR, see c1, Coprocessor Access Control Register (CPACR) on page B3-104.
The SCR, when the Security Extensions are implemented, see c1, Secure Configuration Register
(SCR) on page B3-106.
The TTBCR, see c2, Translation Table Base Control Register (TTBCR) on page B3-117.
The Secure version of the VBAR, when the Security Extensions are implemented, see c12, Vector
Base Address Register (VBAR) on page B3-148.
B3-70 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B