ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
Blocking and non-blocking behavior
The cache block transfer operations for cleaning, invalidating, or clean and invalidating a range of addresses
from the cache are blocking operations. Following instructions must not be executed until the block transfer
operation has completed. The prefetch range operation is non-blocking and can permit following
instructions to be executed before the operation is complete. If an exception occurs a non-blocking operation
does not signal an exception to the processor. This enables implementations to retire following instructions
while the non-blocking operation is executing, without the requirement to retain precise processor state.
The blocking operations generate a Data Abort exception on a Translation fault if a valid translation table
entry cannot be fetched. The DFAR indicates the address that caused the fault, and the DFSR indicates the
reason for the fault.
Any fault on a prefetch range operation results in the operation failing without signaling an error.
Register encodings
Table G-9 shows the block operations supported using CP15. The operations are performed using an MCRR
instruction. See MCRR, MCRR2 on page A8-188.
The instruction format for block operations is:
MCRR p15, , , ,
Note
Table G-9 Enhanced cache control operations using MCRR
CRm Opc Function Rn Data, VA a
c5 0 Invalidate instruction cache range b
a. The true virtual address, before any modification by the FCSE. See Appendix E Fast Context Switch
Extension (FCSE). This address is translated by the FCSE logic.
b. Accessible only in privileged modes. Results in an UNDEFINED instruction exception if the operation is
attempted in user mode.
c. Accessible in both unprivileged and privileged modes.
The ARMv6 MCRR encodings that support block operations are UNDEFINED in ARMv7.
Rt Data, VA a
Start address End address
c6 0 Invalidate data cache range b Start address End address
c12 0 Clean data cache range c
Start address End address
c12 1 Prefetch instruction range c Start address End address
c12 2 Prefetch data range c Start address End address
c14 0 Clean and invalidate data cache range b Start address End address
AppxG-42 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B