ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
Figure B4-9 shows the CP15 c7 cache and branch predictor maintenance operations.
CRn opc1 CRm opc2
c7 0 c1 0 ICIALLUIS, Invalidate all instruction caches to PoU Inner Shareable ‡
6 BPIALLIS, Invalidate entire branch predictor array Inner Shareable ‡
c5 0 ICIALLU, Invalidate all instruction caches to PoU
1 ICIMVAU, Invalidate instruction caches by MVA to PoU
6 BPIALL, Invalidate entire branch predictor array
7 BPIMVA, Invalidate MVA from branch predictor array
c6 1 DCIMVAC, Invalidate data† cache line by MVA to PoC
2 DCISW, Invalidate data† cache line by set/way
c10 1 DCCMVAC, Clean data† cache line by MVA to PoC
2 DCCSW, Clean data† cache line by set/way
c11 1 DCCMVAU, Clean data† cache line by MVA to PoU
c14 1 DCCIMVAC, Clean and invalidate data† cache line by MVA to PoC
2 DCCISW, Clean and invalidate data† cache line by set/way
Read-only Read/Write Write-only † data or unified PoU: Point of Unification
PoC: Point of Coherency
‡ Part of the Multiprocessing Extensions
Figure B4-9 CP15 c7 Cache and branch predictor maintenance operations
The CP15 c7 cache and branch predictor maintenance operations are all write-only operations that can be
executed only in privileged modes. They are listed in Table B4-19.
For more information about the terms used in this section see Terms used in describing cache operations on
page B2-10. The Multiprocessing Extensions changes the set of caches affected by these operations, see
Multiprocessor effects on cache maintenance operations on page B2-23.
In Table B4-19, the Rt data column specifies what data is required in the register Rt specified by the MCR
instruction used to perform the operation. For more information about the possible data formats see Data
formats for the cache and branch predictor operations on page B4-70.
Table B4-19 CP15 c7 cache and branch predictor maintenance operations
CRm opc2 Mnemonic Function a Rt data
c1 0 ICIALLUIS Invalidate all instruction caches to PoU Inner Shareable. Also
flushes branch target cache. b
Ignored
c1 1 BPIALLIS Invalidate entire branch predictor array Inner Shareable. Ignored
c5 0 ICIALLU Invalidate all instruction caches to PoU. Also flushes branch target
cache. c
Ignored
c5 1 ICIMVAU Invalidate instruction cache line by address to PoU. b, d Address
c5 6 BPIALL Invalidate entire branch predictor array. Ignored
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-69