ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

H.6 System level memory model
ARMv4 and ARMv5 Differences
The pseudocode listed in Aligned memory accesses on page B2-31 and Unaligned memory accesses on
page B2-32 covers the alignment behavior of all architecture variants from ARMv4. For ARMv4 and
ARMv5, SCTLR.U is zero, see Alignment on page AppxG-6.
The following sections describe the system level memory model:
Cache support
Tightly Coupled Memory (TCM) support
Virtual memory support
Protected memory support on page AppxH-28.
H.6.1 Cache support
CP15 operations are defined that provide cache operations for managing level 1 instruction, data, or unified
caches. Caches can be direct mapped or N-way associative. ARMv4 and ARMv5 define a Cache Type ID
Register, to enable software to determine the level 1 cache topology.
ARMv4 and ARMv5 support virtual (virtually indexed, virtually tagged) or physical caches. In a virtual
memory system that supports virtual cache or caches, there is no coherence support for virtual aliases that
map to the same physical address. When a virtual to physical address mapping changes, caches must be
cleaned and invalidated accordingly.
Cache management and flushing of any write buffer in the processor is IMPLEMENTATION DEFINED and
managed by CP15. CP15 also supports configuration and control of cache lockdown. For more information
on cache management support see System Control coprocessor (CP15) support on page AppxH-31, and c7,
Cache operations on page AppxH-49 and c9, cache lockdown support on page AppxH-52.
H.6.2 Tightly Coupled Memory (TCM) support
TCM support in ARMv4 and ARMv5 is IMPLEMENTATION DEFINED.
H.6.3 Virtual memory support
The ARMv4 and ARMv5 translation tables support a similar two level translation table format to the
ARMv7 tables. However, there are significant differences in the translation table format because of the
following:
ARMv6 introduced additional bits for encoding memory types, attributes, and extended cache
attributes.
The new translation table format in ARMv6 does not support subpage access permissions.
ARMv4 does not support 16MB Supersections.
Only ARMv4 and ARMv5 support tiny (1KB) pages. The fine second level page format is not
supported from ARMv6.
For general information about address translation in a VMSA, see About the VMSA on page B3-2
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxH-21