ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A6.3.3 Data-processing (plain binary immediate)
Thumb Instruction Set Encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 op Rn 0
Table A6-12 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
These encodings are all available in ARMv6T2 and above.
Table A6-12 32-bit unmodified immediate data-processing instructions
op Rn Instruction See
00000 not 1111 Add Wide (12-bit) ADD (immediate, Thumb) on page A8-20
1111 Form PC-relative Address ADR on page A8-32
00100 - Move Wide (16-bit) MOV (immediate) on page A8-194
01010 not 1111 Subtract Wide (12-bit) SUB (immediate, Thumb) on page A8-418
1111 Form PC-relative Address ADR on page A8-32
01100 - Move Top (16-bit) MOVT on page A8-200
100x0 a
10010 b
- Signed Saturate SSAT on page A8-362
- Signed Saturate (two 16-bit) SSAT16 on page A8-364
10100 - Signed Bit Field Extract SBFX on page A8-308
10110 not 1111 Bit Field Insert BFI on page A8-48
1111 Bit Field Clear BFC on page A8-46
110x0 a - Unsigned Saturate USAT on page A8-504
11010 b - Unsigned Saturate 16 USAT16 on page A8-506
11100 - Unsigned Bit Field Extract UBFX on page A8-466
a. In the second halfword of the instruction, bits [14:12.7:6] != 0b00000.
b. In the second halfword of the instruction, bits [14:12.7:6] == 0b00000.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A6-19