ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

C5.8.1 Access to specific cache management functions in Debug state
Debug State
If a processor includes the Security Extensions and supports Secure User halting debug, it must implement
mechanisms that enable memory system requirements to be met when debugging in Secure User mode when
invasive debug is not permitted in Secure privileged modes. This is a situation where executing the CP15
cache and TLB control operations would otherwise be prohibited.
To meet these requirements, ARM recommends that, on a processor that implements the Security
Extensions and supports Secure User halting debug, when the processor is in Debug state:
the rules for accessing CP15 registers do not apply for a certain set of register access operations
the set of operations depends on the Debug architecture version, as shown in Table C5-5.
Versions Operation Description
Table C5-5 CP15 operations permitted from User mode in Debug state
v7 Debug MCR p15,0,,c7,c5,0 Invalidate entire instruction cache and flush branch predictor arrays a
MCR p15,0,,c7,c5,1 Invalidate instruction cache by MVA a
MCR p15,0,,c7,c5,7 Invalidate MVA from branch predictor array
MCR p15,0,,c7,c10,1 Clean data or unified cache line by MVA to point of coherency b
MCR p15,0,,c7,c10,2 Clean data or unified cache line by set/way b
MCR p15,0,,c7,c11,1 Clean data or unified cache line by MVA to point of unification b
MCR p15,0,,c7,c1,0 Invalidate entire instruction cache Inner Shareable c
MCR p15,0,,c7,c1,6 Invalidate entire branch predictor array Inner Shareable c
v6.1 Debug MCRR p15,0,,,c5 Invalidate instruction cache by VA range
v6.1 Debug,
v7 Debug
MCR p15,0,,c7,c5,6 Flush entire branch predictor array
a. See also v7 Debug restrictions on instruction cache invalidation in Secure User debug on page C5-26.
b. A debugger does not have to perform cache cleaning operations if DBGDSCCR.nWT is implemented and is set to 0,
see Debug State Cache Control Register (DBGDSCCR) on page C10-81. This is because when nWT is set to 0, writes
do not leave dirty data in the cache that is not coherent with outer levels of memory. However, the I-cache is not updated,
so I-cache invalidate operations are required.
c. These instructions are part of the Multiprocessing Extensions. See Multiprocessor effects on cache maintenance
operations on page B2-23.
These instructions must be executable in Debug state regardless of any processor setting. However, use of
an operation can generate an abort if instruction cache lockdown is in use.
For more information about debug access to coprocessor instructions, see Coprocessor and Advanced SIMD
instructions in Debug state on page C5-16.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C5-25