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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Assembler syntax<br />

Instruction Details<br />

VPADD.F32 {,} , Encoded as Q = 0, sz = 0<br />

where:<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7. An <strong>ARM</strong> VPADD instruction<br />

must be unconditional.<br />

, , The destination vector, the first oper<strong>and</strong> vector, <strong>and</strong> the second oper<strong>and</strong> vector.<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations(); CheckAdvSIMDEnabled();<br />

bits(64) dest;<br />

h = elements/2;<br />

for e = 0 to h-1<br />

Elem[dest,e,esize] = FPAdd(Elem[D[n],2*e,esize], Elem[D[n],2*e+1,esize], FALSE);<br />

Elem[dest,e+h,esize] = FPAdd(Elem[D[m],2*e,esize], Elem[D[m],2*e+1,esize], FALSE);<br />

D[d] = dest;<br />

Exceptions<br />

Undefined Instruction.<br />

Floating-point exceptions: Input Denormal, Invalid Operation, Overflow, Underflow, <strong>and</strong> Inexact.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A8-687

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