ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.1.6 Exception information
A8.1.7 Notes
The Exceptions subsection contains a list of the exceptional conditions that can be caused by execution of
the instruction.
Processor exceptions are listed as follows:
Resets and interrupts (both IRQs and FIQs) are not listed. They can occur before or after the
execution of any instruction, and in some cases during the execution of an instruction, but they are
not in general caused by the instruction concerned.
Prefetch Abort exceptions are normally caused by a memory abort when an instruction is fetched,
followed by an attempt to execute that instruction. This can happen for any instruction, but is caused
by the aborted attempt to fetch the instruction rather than by the instruction itself, and so is not listed.
A special case is the BKPT instruction, that is defined as causing a Prefetch Abort exception in some
circumstances.
Data Abort exceptions are listed for all instructions that perform data memory accesses.
Undefined Instruction exceptions are listed when they are part of the effects of a defined instruction.
For example, all coprocessor instructions are defined to produce the Undefined Instruction exception
if not accepted by their coprocessor. Undefined Instruction exceptions caused by the execution of an
UNDEFINED instruction are not listed, even when the UNDEFINED instruction is a special case of one
or more of the encodings of the instruction. Such special cases are instead indicated in the
encoding-specific pseudocode for the encoding.
Supervisor Call and Secure Monitor Call exceptions are listed for the SVC and SMC instructions
respectively. Supervisor Call exceptions and the SVC instruction were previously called Software
Interrupt exceptions and the SWI instruction. Secure Monitor Call exceptions and the SMC instruction
were previously called Secure Monitor interrupts and the SMI instruction.
Floating-point exceptions are listed for instructions that can produce them. Floating-point exceptions on
page A2-42 describes these exceptions. They do not normally result in processor exceptions.
Where appropriate, other notes about the instruction appear under additional subheadings.
Note
Information that was documented in notes in previous versions of the ARM Architecture Reference Manual
and its supplements has often been moved elsewhere. For example, operand restrictions on the values of
bitfields in an instruction encoding are now normally documented in the encoding-specific pseudocode for
that encoding.
A8-6 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B