ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.12.9 c0, TCM Type Register (TCMTR)
Virtual Memory System Architecture (VMSA)
The TCM Type Register, TCMTR, provides information about the implementation of the TCM.
The TCMTR is:
a 32-bit read-only register
accessible only in privileged modes.
when the Security Extensions are implemented, a Common register.
From ARMv7:
TCMTR must be implemented
when the ARMv7 format is used, the meaning of register bits [28:0] is IMPLEMENTATION DEFINED
the ARMv6 format of the TCM Type Register remains a valid usage model
if no TCMs are implemented the ARMv6 format must be used to indicate zero-sized TCMs.
The ARMv7 format of the TCMTR is:
31 29 28 0
1 0 0 IMPLEMENTATION DEFINED
Bits [31:29] Set to 0b100 for the ARMv7 register format.
Note
This field is set to 0b000 for the format used in ARMv6 and earlier.
Bits [28:0] IMPLEMENTATION DEFINED in the ARMv7 register format.
If no TCMs are implemented, the TCMTR must be implemented with this ARMv6 format:
31 29 28 19 18 16 15 3 2 0
0 0 0 UNKNOWN 0 0 0 UNKNOWN 0 0 0
For details of the ARMv6 optional implementation of the TCM Type Register see c0, TCM Type Register
(TCMTR) on page AppxG-33.
Accessing the TCMTR
To access the TCMTR you read the CP15 registers with set to 0, set to c0, set to c0, and
set to 2. For example:
MRC p15,0,,c0,c0,2 ; Read CP15 TCM Type Register
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-85