ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
The format of the PMINTENCLR Register is:
31 30 N N-1 0
C RAZ/WI Event counter overflow interrupt disable bits, Px, for x = 0 to (N-1)
Note
In the description of the PMINTENCLR Register, N and x have the meanings used in the description of the
PMINTENSET Register, see c9, Interrupt Enable Set Register (PMINTENSET) on page C10-118.
C, bit [31] PMCCNTR overflow interrupt disable bit.
See Table C10-29 for the behavior of this bit on reads and writes.
Bits [30:N] RAZ/WI.
Pm, bit [x], for x = 0 to (N-1)
Event counter x, PMNx, overflow interrupt disable bit.
Table C10-29 shows the behavior of this bit on reads and writes.
Table C10-29 Read and write bit values for the PMINTENCLR Register
Value Meaning on read Action on write
0 Interrupt disabled No action, write is ignored
1 Interrupt enabled Disable interrupt
The contents of the PMINTENCLR Register are UNKNOWN on a core logic reset.
For more information about counter overflow interrupts see c9, Interrupt Enable Set Register
(PMINTENSET) on page C10-118.
C10-120 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B