ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
0b0010 Cache, TLB and branch predictor operations affect structures according to
shareability an defined behavior of instructions.
BP maintain, bits [11:8]
Indicates the supported branch predictor maintenance operations in an implementation with
hierarchical cache maintenance operations. Permitted values are:
0b0000 None supported.
0b0001 Supported branch predictor maintenance operations are:
Invalidate entire branch predictor array
0b0010 As for 0b0001, and adds:
Invalidate branch predictor by MVA.
Cache maintain s/w, bits [7:4]
Indicates the supported cache maintenance operations by set/way, in an implementation
with hierarchical caches. Permitted values are:
0b0000 None supported.
0b0001 Supported hierarchical cache maintenance operations by set/way are:
Invalidate data cache by set/way
Clean data cache by set/way
Clean and invalidate data cache by set/way.
In a unified cache implementation, the data cache operations apply to the unified caches.
Cache maintain MVA, bits [3:0]
Indicates the supported cache maintenance operations by MVA, in an implementation with
hierarchical caches. Permitted values are:
0b0000 None supported.
0b0001 Supported hierarchical cache maintenance operations by MVA are:
Invalidate data cache by MVA
Clean data cache by MVA
Clean and invalidate data cache by MVA
Invalidate instruction cache by MVA
Invalidate all instruction cache entries.
In a unified cache implementation, the data cache operations apply to the unified caches, and
the instruction cache operations are not implemented.
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