ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
The registers containing the structure. Encoded with D:Vd = . It must be one of:
{, , }
Single-spaced registers, see Table A8-7.
{, , }
Double-spaced registers, see Table A8-7. This is not available if == 8.
Contains the base address for the access.
! If present, specifies writeback.
Contains an address offset applied after the access.
For more information about , !, and , see Advanced SIMD addressing mode on page A7-30.
Alignment
Standard alignment rules apply, see Unaligned data access on page A3-5.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
address = R[n];
if wback then R[n] = R[n] + (if register_index then R[m] else 3*ebytes);
Elem[D[d],index,esize] = MemU[address,ebytes];
Elem[D[d2],index,esize] = MemU[address+ebytes,ebytes];
Elem[D[d3],index,esize] = MemU[address+2*ebytes,ebytes];
Exceptions
Undefined Instruction, Data Abort.
Table A8-7 Encoding of index and register spacing
== 8 == 16 == 32
Index index_align[3:1] = x index_align[3:2] = x index_align[3] = x
Single-spacing index_align[0] = 0 index_align[1:0] = '00' index_align[2:0] = '000'
Double-spacing - index_align[1:0] = '10' index_align[2:0] = '100'
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-617