ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
Accessing the execution state bits
The execution state bits are the IT[7:0], J, E, and T bits. In exception modes you can read or write these bits
in the current SPSR.
In the CPSR, unless the processor is in Debug state:
The execution state bits, other than the E bit, are RAZ when read by an MRS instruction.
Writes to the execution state bits, other than the E bit, by an MSR instruction are:
— For ARMv7 and ARMv6T2, ignored in all modes.
— For architecture variants before ARMv6T2, ignored in User mode and required to write zeros
in privileged modes. If a nonzero value is written in a privileged mode, behavior is
UNPREDICTABLE.
Instructions other than MRS and MSR that access the execution state bits can read and write them in any mode.
Unlike the other execution state bits in the CPSR, CPSR.E can be read by an MRS instruction and written by
an MSR instruction. However, using the CPSR.E value read by an MRS instruction is deprecated, and using an
MSR instruction to change the value of CPSR.E is deprecated.
Note
Use the SETEND instruction to change the current endianness.
To determine the current endianness, use an LDR instruction to load a word of memory whose value is
known and will differ if the endianness is reversed. For example, use an LDR (literal) instruction to
load a word whose four bytes are 0x01, 0x00, 0x00, and 0x00 in ascending order of memory address.
The LDR instruction loads the destination register with:
— 0x00000001 if the current endianness is little-endian
— 0x01000000 if the current endianness is big-endian.
For more information about the behavior of these bits in Debug state see Behavior of the PC and CPSR in
Debug state on page C5-7.
Non-maskable fast interrupts
Exceptions, debug events and checks on page A2-81 introduces the two levels of external interrupts to an
ARM processor, Interrupt Requests or IRQs and higher priority Fast Interrupt Requests or FIQs. Both IRQs
and FIQs can be masked by bits in the CPSR, see Program Status Registers (PSRs) on page B1-14:
when the CPSR.I bit is set to 1, IRQ interrupts are masked
when the CPSR.F bit is set to 1, FIQ interrupts are masked.
ARMv7 supports an operating mode where FIQs are not maskable by software. This Non-maskable Fast
Interrupt (NMFI) operation is controlled by a configuration input signal to the processor, that is asserted
HIGH to enable NMFI operation. There is no software control of NMFI operation.
Software can detect whether FIQs are maskable by reading the SCTLR.NMFI bit:
NMFI == 0 Software can mask FIQs by setting the CPSR.F bit to 1
NMFI == 1 Software cannot mask FIQs.
B1-18 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B