ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VEXT. {,} , , # Encoded as Q = 1
VEXT. {,} , , # Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VEXT instruction must
be unconditional.
Size of the operation. The value can be:
8, 16, or 32 for doubleword operations
8, 16, 32, or 64 for quadword operations.
If the value is 16, 32, or 64, the syntax is a pseudo-instruction for a VEXT instruction
specifying the equivalent number of bytes. The following examples show how an
assembler treats values greater than 8:
VEXT.16 D0,D1,#x is treated as VEXT.8 D0,D1,#(x*2)
VEXT.32 D0,D1,#x is treated as VEXT.8 D0,D1,#(x*4)
VEXT.64 Q0,Q1,#x is treated as VEXT.8 Q0,Q1,#(x*8).
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
The location of the extracted result in the concatenation of the operands, as a
number of bytes from the least significant end, in the range 0-7 for a doubleword
operation or 0-15 for a quadword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
if quadword_operation then
Q[d] = (Q[m]:Q[n]);
else
D[d] = (D[m]:D[n]);
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-599