ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Thumb Instruction Set Encoding
A6.3.14 Parallel addition and subtraction, unsigned
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 0 1 op1 1 1 1 1 0 1 op2
If, in the second halfword of the instruction, bits [15:12] != 0b1111, the instruction is UNDEFINED.
Table A6-25 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
These encodings are all available in ARMv6T2 and above.
Table A6-25 Unsigned parallel addition and subtraction instructions
op1 op2 Instruction See
001 00 Add 16-bit UADD16 on page A8-460
010 00 Add, Subtract UASX on page A8-464
110 00 Subtract, Add USAX on page A8-508
101 00 Subtract 16-bit USUB16 on page A8-510
000 00 Add 8-bit UADD8 on page A8-462
100 00 Subtract 8-bit USUB8 on page A8-512
Saturating instructions
001 01 Saturating Add 16-bit UQADD16 on page A8-488
010 01 Saturating Add, Subtract UQASX on page A8-492
110 01 Saturating Subtract, Add UQSAX on page A8-494
101 01 Saturating Subtract 16-bit UQSUB16 on page A8-496
000 01 Saturating Add 8-bit UQADD8 on page A8-490
100 01 Saturating Subtract 8-bit UQSUB8 on page A8-498
Halving instructions
001 10 Halving Add 16-bit UHADD16 on page A8-470
010 10 Halving Add, Subtract UHASX on page A8-474
110 10 Halving Subtract, Add UHSAX on page A8-476
101 10 Halving Subtract 16-bit UHSUB16 on page A8-478
000 10 Halving Add 8-bit UHADD8 on page A8-472
100 10 Halving Subtract 8-bit UHSUB8 on page A8-480
A6-36 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B