ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.231 TST (register)
Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value.
It updates the condition flags based on the result, and discards the result.
Encoding T1 ARMv4T, ARMv5T*, ARMv6*, ARMv7
TST ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 1 0 0 0 Rm Rn
n = UInt(Rdn); m = UInt(Rm);
(shift_t, shift_n) = (SRType_LSL, 0);
Encoding T2 ARMv6T2, ARMv7
TST.W ,{,}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 1 0 0 0 0 1 Rn (0) imm3 1 1 1 1 imm2 type Rm
n = UInt(Rn); m = UInt(Rm);
(shift_t, shift_n) = DecodeImmShift(type, imm3:imm2);
if BadReg(n) || BadReg(m) then UNPREDICTABLE;
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
TST ,{,}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 0 0 0 1 Rn (0) (0) (0) (0) imm5 type 0 Rm
n = UInt(Rn); m = UInt(Rm);
(shift_t, shift_n) = DecodeImmShift(type, imm5);
A8-456 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B