ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv6 Differences
G.7.3 c0, ID support
ARMv6 implementations include a Main ID Register, see c0, Main ID Register (MIDR) on page B3-81. In
this register, the architecture variant field either takes the assigned ARMv6 value or indicates support for an
identification scheme based on a set of CPUID registers. The CPUID identification scheme is required in
ARMv7 and recommended for ARMv6, and is described in Chapter B5 The CPUID Identification Scheme.
Three other ID registers provide information about cache, TCM, and TLB provisions. From ARMv6K, there
is also a Multiprocessor Affinity Register.
All of the CP15 c0 ID registers are read-only registers, They are accessed using MRC instructions, as shown
in Table G-5.
The Cache Type Register is as defined for ARMv4 and ARMv5, see c0, Cache Type Register (CTR) on
page AppxH-35. In ARMv6, the CType values of 0b0110, and 0b0111 are reserved and must not be used.
Note
Table G-5 ID register support
Register CRn opc1 CRm opc2
MIDR, Main ID Register c0 0 c0 0
CTR, Cache Type ID Register c0 0 c0 1
TCMTR, TCM Type Register c0 0 c0 2
TLBTR, TLB Type Register a
c0 0 c0 3
MPUIR, MPU Type Register c c0 0 c0 4
MPIDR, Multiprocessor Affinity Register b
c0 0 c0 5
Aliases of MIDR c0 0 c0 3 c, 4 a, 5 d, 6, 7
CPUID registers, if implemented c0 0 c1 0-7
c0 0 c2 0-5
a. VMSA processors only.
b. ARMv6K processors with VMSA only.
c. PMSA processors only.
d. All ARMv6 processors except ARMv6K VMSA implementations.
The ARMv6 format of the Cache Type Register is significantly different from the ARMv7 implementation
described in c0, Cache Type Register (CTR) on page B3-83. However, the general properties described by
the register, and the access rights for the register, are unchanged.
The TCM Type Register is defined in c0, TCM Type Register (TCMTR) on page AppxG-33.
AppxG-32 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B