ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
1 If a TLB miss occurs when TTBR1 is used no translation table walk is
performed and a Section Translation fault is returned.
PD0, bit [4], when Security Extensions are implemented
Translation table walk Disable bit for TTBR0. This bit controls whether a translation table
walk is performed on a TLB miss when TTBR0 is used. The meanings of the possible values
of this bit are equivalent to those for the PD1 bit.
Bits [5:4], when Security Extensions are not implemented
UNK/SBZP.
N, bits [2:0] Indicate the width of the base address held in TTBR0. In TTBR0, the base address field is
bits [31:14-N]. The value of N also determines:
whether TTBR0 or TTBR1 is used as the base address for translation table walks.
the size of the translation table pointed to by TTBR0.
N can take any value from 0 to 7, that is, from 0b000 to 0b111.
When N has its reset value of 0, the translation table base is compatible with ARMv5 and
ARMv6.
Determining which TTBR to use, and the TTBR0 translation table size
When an MVA is not found in the TLB, the value of TTBCR.N determines whether TTBR0 or TTBR1 is
used as the base address for the translation table walk in memory:
if N == 0 then always use TTBR0
if N > 0 then:
— if bits [31:32-N] of the MVA are all zero then use TTBR0
— otherwise use TTBR1.
The size of the first-level translation tables accessed by TTBR0 depends on the value of TTBCR.N as shown
in Table B3-29:
Table B3-29 Value of N field and the size of the TTBR0 translation table
TTBCR.N Size of TTBR0 translation table
0b000 16KB
0b001 8KB
0b010 4KB
0b011 2KB
0b100 1KB
B3-118 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B