ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
Translation flow for a Supersection
Figure B3-5 shows the virtual to physical addresses translation for a Supersection. For details of the
extended Supersection address and access control fields in the first-level descriptor see the Supersection
entry in Table B3-1 on page B3-8.
Translation Table
Base Register
MVA
PA31:0] of
first-level descriptor
PA[39:32] = 0x00
First-level
Supersection descriptor
31 14-N 13-N
Translation base SBZ
31 32-N 31-N 24 23 20 19
31 14-N 13-N 2 1
Translation base Table index 0 0
First-level
read
Figure B3-5 Supersection address translation
Note
Figure B3-5 shows how, when the MVA addresses a Supersection, the top four bits of the Supersection index
bits of the MVA overlap the bottom four bits of the Table index bits. For more information, see Additional
requirements for translation tables on page B3-11.
B3-18 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B
31
Supersection
base address
32 31 24 23
PA[39:0]
Extended Supersection
base address base address
For a translation based on TTBR0, N is the value of TTBCR.N
For a translation based on TTBR1, N is 0
‡ This field is absent if N==0
39
‡
Table index
24 23
0
0
Supersection index
Extended Supersection base address
and Access control fields
Supersection index
2 1
0
0
1 0
0