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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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The System Level Programmers’ Model<br />

return;<br />

// SPSRWriteByInstr()<br />

// ==================<br />

if !IsSecure() && value == ‘10001’ && NSACR.RFR == ‘1’ then UNPREDICTABLE;<br />

CPSR = value; // M mode bits<br />

SPSRWriteByInstr(bits(32) value, bits(4) bytemask)<br />

if CurrentModeIsUserOrSystem() then UNPREDICTABLE;<br />

if bytemask == ‘1’ then<br />

SPSR[] = value; // N,Z,C,V,Q flags, IT,J execution state bits<br />

if bytemask == ‘1’ then<br />

// bits are reserved SBZP bits<br />

SPSR[] = value; // GE flags<br />

if bytemask == ‘1’ then<br />

SPSR[] = value; // IT execution state bits, E bit, A interrupt mask<br />

if bytemask == ‘1’ then<br />

SPSR[] = value; // I,F interrupt masks, T execution state bit<br />

if BadMode(value) then // Mode bits<br />

UNPREDICTABLE;<br />

else<br />

SPSR[] = value;<br />

return;<br />

B1-22 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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